A54SX08-1BG208 ETC1 [List of Unclassifed Manufacturers], A54SX08-1BG208 Datasheet - Page 24

• Manufacturer Part Number: A54SX08-1BG208
• Description: 54SX Family FPGAs
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

R e g i s t e r C el l T i m i n g C h a ra c t er i s ti c s
Fl ip -F lo ps
T i m i n g C h a ra c t er i s ti c s
Timing characteristics for 54SX devices fall into three
categories:
design-dependent.
characteristics are common to all 54SX family members.
Internal routing delays are device dependent. Design
dependency means actual delays are not determined until
after placement and routing of the user’s design is complete.
Delay values may then be determined by using the
DirectTime Analyzer utility or performing simulation with
post-layout delays.
C r i t ic al N e t s a nd T yp ic a l N e t s
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
time-critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up to
6% of the nets in a design may be designated as critical,
while 90% of the nets in a design are typical.
T em p er a tu r e an d V o l t a ge D er a ti ng F a c to r s
(Normalized to Worst-Case Commercial, T
24
V
PRESET
3.0
3.3
3.6
CCA
CLR
CLK
Q
D
family-dependent,
The
0.75
0.70
0.66
–55
t
SUD
input
device-dependent,
and
0.78
0.73
0.69
–40
output
t
t
CLK
HPWH
RPWH
(Positive edge triggered)
0.87
0.82
0.77
D
buffer
J
0
and
= 70°C, V
,
Junction Temperature (T
t
PRESET
HD
v3.1
CLR
t
RCO
L on g T r a c ks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules. Long tracks employ three and sometimes five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically up to 6% of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is
represented statistically in higher fanout (FO=24) routing
delays in the data sheet specifications section.
T i m i n g D e r a t i n g
54SX devices are manufactured in a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
CCA
0.89
0.83
0.78
25
t
t
HPWL
RPWL
Q
= 3.0V)
t
,
t
WASYN
CLR
J
)
1.00
0.93
0.87
70
t
HP
t
PRESET
5 4 S X F a m i l y F P G A s
1.04
0.97
0.92
85
1.16
1.08
1.02
125