AGLE3000V2-FFG896 ACTEL [Actel Corporation], AGLE3000V2-FFG896 Datasheet - Page 101
![no-image](/images/no-image-200.jpg)
AGLE3000V2-FFG896
Manufacturer Part Number
AGLE3000V2-FFG896
Description
IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.AGLE3000V2-FFG896.pdf
(156 pages)
- Current page: 101 of 156
- Download datasheet (6Mb)
Figure 2-38 • Timing Model and Waveforms
Table 2-129 • Register Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
CLK
Data
EN
Out
CLKQ
SUD
HD
SUE
HE
CLR2Q
PRE2Q
REMCLR
RECCLR
REMPRE
RECPRE
WCLR
WPRE
CKMPWH
CKMPWL
PRE
CLR
For specific junction temperature and voltage supply levels, refer to
values.
Timing Characteristics
1.5 V DC Core Voltage
Commercial-Case Conditions: T
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
50%
50%
t
SUE
t
HE
50%
t
CLKQ
50%
t
SUD
0
t
HD
t
50%
PRE2Q
50%
J
50%
t
= 70°C, Worst-Case V
WPRE
A dv a n c e v 0. 3
50%
Description
50%
50%
t
t
RECPRE
WCLR
50%
t
50%
50%
CLR2Q
CC
50%
= 1.425 V
t
RECCLR
IGLOOe DC and Switching Characteristics
Table 2-6 on page 2-6
50%
t
CKMPWH
t
50%
REMPRE
t
50%
CKMPWL
0.89
0.81
0.00
0.73
0.00
0.60
0.62
0.00
0.24
0.00
0.23
0.30
0.30
0.56
0.56
Std.
for derating
50%
50%
t
REMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2 - 87
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