XR16M554DIV64 EXAR [Exar Corporation], XR16M554DIV64 Datasheet - Page 45

• Manufacturer Part Number: XR16M554DIV64
• Description: 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

REV. 1.0.0
GENERAL DESCRIPTION................................................................................................ 1
PIN DESCRIPTIONS ......................................................................................................... 4
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 9
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 10
3.0 UART INTERNAL REGISTERS............................................................................................................. 19
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 20
F
A
ORDERING INFORMATION
EATURES
PPLICATIONS
2.1 CPU INTERFACE .............................................................................................................................................. 10
2.2 DEVICE RESET ................................................................................................................................................. 11
2.3 CHANNEL SELECTION .................................................................................................................................... 11
2.4 CHANNELS A-D INTERNAL REGISTERS ....................................................................................................... 12
2.5 INT OUPUTS FOR CHANNELS A-D................................................................................................................. 12
2.6 DMA MODE ....................................................................................................................................................... 12
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 13
2.8 PROGRAMMABLE BAUD RATE GENERATOR.............................................................................................. 13
2.9 TRANSMITTER.................................................................................................................................................. 14
2.10 RECEIVER ....................................................................................................................................................... 16
2.11 INTERNAL LOOPBACK................................................................................................................................. 18
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 20
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 20
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 20
4.4 INTERRUPT STATUS REGISTER (ISR)........................................................................................................... 22
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 23
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 24
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE . 25
4.8 LINE STATUS REGISTER (LSR) - READ/WRITE ............................................................................................ 26
4.9 MODEM STATUS REGISTER (MSR) - READ/WRITE...................................................................................... 27
F
F
F
F
T
T
T
T
T
F
F
T
F
F
F
F
F
T
T
T
T
T
T
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 15
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 15
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 15
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 16
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 21
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 21
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 22
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 22
1: C
2: C
3: INT P
4: INT P
5: TXRDY#
6: T
7: UART CHANNEL A AND B UART INTERNAL REGISTERS ...................................................................................... 19
8: INTERNAL REGISTERS DESCRIPTION. ................................................................................................................... 20
9: I
10: R
11: P
12: INT O
1. XR16M554 B
2. P
3. P
4. XR16M554 T
5. T
6. B
7. T
8. T
9. R
10. R
11. I
.................................................................................................................................................... 1
NTERRUPT
YPICAL DATA RATES WITH A
HANNEL
HANNEL
YPICAL
RANSMITTER
RANSMITTER
IN
IN
AUD
ECEIVER
ECEIVE
ARITY SELECTION
NTERNAL
ECEIVER
.............................................................................................................................................. 1
O
O
IN
IN
UT
UT
R
UTPUT
O
O
ATE
A-D S
A-D S
AND
C
A
A
PERATION FOR
PERATION FOR
FIFO T
RYSTAL
S
SSIGNMENT
SSIGNMENT
O
L
O
OURCE AND
G
PERATION IN NON
OOP
RXRDY# O
M
YPICAL
PERATION IN
LOCK
ENERATOR
O
O
ELECT IN
ELECT IN
ODES
............................................................................................................................... 4
PERATION IN NON
PERATION IN
RIGGER
B
C
ACK IN
........................................................................................................................................................ 25
D
ONNECTIONS
I
IAGRAM
..................................................................................................................................................... 26
NTEL
F
F
OR
OR
T
R
P
16 M
68 M
............................................................................................................................................... 14
L
UTPUTS IN
RANSMITTER FOR
RIORITY
ECEIVER FOR
C
EVEL
FIFO.................................................................................................................................... 17
/M
68-
48-
14.7456 MH
HANNELS
FIFO
OTOROLA
.......................................................................................................................................... 1
-FIFO M
ODE
ODE
PIN
PIN
TABLE OF CONTENTS
S
-FIFO M
.................................................................................................................................. 13
ELECTION
L
PLCC P
QFN P
................................................................................................................................. 11
................................................................................................................................. 11
AND
EVEL
FIFO
A - D ................................................................................................................... 18
ODE
D
C
F
Z CRYSTAL OR EXTERNAL CLOCK
ATA
HANNELS
LOW
....................................................................................................................... 22
ACKAGE AND
ODE
AND
.................................................................................................................... 16
ACKAGES
C
................................................................................................................... 23
HANNELS
B
C
.............................................................................................................. 15
US
DMA M
ONTROL
I
A-D ................................................................................................. 12
NTERCONNECTIONS
1
I
N
A-D ........................................................................................... 12
ODE FOR
80-
16
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
M
ODE
PIN
AND
LQFP P
..................................................................................... 15
68 M
C
HANNELS
ODE AND
.......................................................................... 10
ACKAGE
...................................................................... 14
A-D ........................................................... 13
64-
............................................................... 3
PIN
LQFP P
ACKAGES
XR16M554/554D
......................... 2