XR16M554DIV64 EXAR [Exar Corporation], XR16M554DIV64 Datasheet
XR16M554DIV64
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XR16M554DIV64 Summary of contents
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MAY 2008 GENERAL DESCRIPTION The XR16M554 (M554 quad Universal Asynchronous Receiver and Transmitter (UART) with 16 bytes of transmit and receive FIFOs, selectable receive FIFO trigger levels and data rates Mbps at 3.3 V. ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO IGURE IN UT SSIGNMENT OR DSRA# 10 CTSA# 11 DTRA VCC RTSA INTA XR16M554 CSA# 16 68-pin PLCC TXA 17 IOW# ...
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REV. 1.0 IGURE IN UT SSIGNMENT OR CTSA# 1 VCC 2 RTSA# 3 INTA 4 CSA# 5 XR16M554 TXA 6 48-pin QFN IOW# 7 Intel Mode (16/68# pin connected to VCC) TXB 8 CSB# ...
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... XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO ORDERING INFORMATION P N ART UMBER XR16M554IJ68 XR16M554IV64 XR16M554DIV64 XR16M554IL48 XR16M554IV80 PIN DESCRIPTIONS Pin Description 48-QFN 64-LQFP 68-PLCC N AME DATA BUS INTERFACE ...
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REV. 1.0.0 Pin Description 48-QFN 64-LQFP 68-PLCC N AME CSB (A3) CSC (A4) CSD (VCC) INTA 4 6 (IRQ#) INTB 10 12 INTC 26 37 INTD 32 43 ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO Pin Description 48-QFN 64-LQFP 68-PLCC N AME INTSEL 38 - MODEM OR SERIAL I/O INTERFACE TXA 6 8 TXB 8 10 TXC 28 39 TXD ...
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REV. 1.0.0 Pin Description 48-QFN 64-LQFP 68-PLCC N AME CDA CDB CDC CDD RIA RIB RIC RID ANCILLARY ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO Pin Description 48-QFN 64-LQFP 68-PLCC N AME N. Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. 80-LQFP T YPE ...
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REV. 1.0.0 1.0 PRODUCT DESCRIPTION The XR16M554 (M554) integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver and Transmitter (UART). Each UART is independently controlled and has its own set of device configuration registers. The configuration registers set is ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The M554 ...
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REV. 1.0.0 2.2 Device Reset The RESET input resets the internal registers and the serial interface outputs in all channels to their default state (see Table 13). An active high pulse of longer than 40 ns duration will be required ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO 2.4 Channels A-D Internal Registers Each UART channel in the M554 has a set of enhanced registers for controlling, monitoring and data loading and unloading. The configuration register set is compatible ...
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REV. 1.0 TXRDY# RXRDY# O ABLE AND FCR -0=0 BIT P INS (FIFO D ) ISABLED RXRDY# LOW = 1 byte HIGH = no data TXRDY# LOW = THR empty HIGH = byte in THR 2.7 Crystal Oscillator ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO IGURE AUD ATE ENERATOR Crystal XTAL1 Osc / XTAL2 Buffer ABLE YPICAL DATA RATES WITH A O Data Rate UTPUT D IVISOR FOR ...
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REV. 1.0.0 2.9.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO 2.10 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock ...
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REV. 1.0 IGURE ECEIVER PERATION IN 16X C lock R eceive D ata Shift R egister ( bytes by 11-bit w ide FIFO R eceive D ata Byte and Errors 1.62V TO 3.63V ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO 2.11 Internal Loopback The M554 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular ...
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REV. 1.0.0 3.0 UART INTERNAL REGISTERS Each UART channel in the M554 has its own set of configuration registers selected by address lines A0, A1 and A2 with a specific channel selected (See Table 7 and Table ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO T ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit ...
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REV. 1.0.0 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT and receive interrupts (IER BIT are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect the ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO 4.4 Interrupt Status Register (ISR) The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. ...
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REV. 1.0.0 ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. 4.5 FIFO Control Register (FCR) - Write-Only This register ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and ...
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REV. 1.0.0 LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and LCR ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO MCR[3]: INT Output Enable Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL input, see below table for details. This bit is ...
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REV. 1.0.0 LSR[4]: Receive Break Tag • Logic break condition (default). • Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the FIFO mode, only one ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO MSR[4]: CTS Input Status A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW will resume data transmission. Normally ...
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REV. 1.0.0 T 13: UART RESET CONDITIONS FOR CHANNELS A-D ABLE REGISTERS DLM, DLL RHR THR IER FCR ISR LCR MCR LSR MSR SPR I/O SIGNALS TX RTS# DTR# RXRDY# TXRDY# INT (16 Mode) IRQ# (68 Mode) 1.62V TO 3.63V ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-QFN) Thermal Resistance (64-LQFP) Thermal Resistance (68-PLCC) Thermal ...
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REV. 1.0.0 AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER XTAL1 UART Crystal Frequency ECLK External Clock Frequency T External Clock Time Period ECLK T Address Setup Time ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER T Delay To Reset Interrupt From IOR# RSI T Delay From ...
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REV. 1.0 IGURE ODEM NPUT UTPUT ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO F 15 IGURE ODE NTEL ATA A0-A7 Valid Address T AS CS# IOW# D0- IGURE ODE OTOROLA A0-A7 Valid ...
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REV. 1.0 IGURE ODE OTOROLA A0-A7 Valid Address T ADS CS# T RWS R/W# D0- & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO F 19 & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data ...
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REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT Start Stop Bit Bit RX S D0:D7 S D0:D7 INT RX FIFO fills Trigger Level or RX Data Timeout RXRDY# IOR# (Reading data out of ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO F 23 & I IGURE RANSMIT EADY NTERRUPT Stop Start Bit Bit TX S D0:D7 S D0:D7 T (Unloading) IER[1] ISR Read enabled INT* TXRDY# IOW# (Loading data into ...
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REV. 1.0.0 PACKAGE DIMENSIONS 48 LEAD QUAD FLAT NO LEAD ( 0.9 mm, 0.50 mm pitch QFN) Note: The control dimension is the millimeter column SYMBOL 1.62V TO ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO 64 LEAD LOW-PROFILE QUAD FLAT PACK ( 1.4 mm LQFP) A Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
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REV. 1.0.0 68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC Note: The control dimension is the inch column SYMBOL ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO 80 LEAD PLASTIC QUAD FLAT PACK ( LQFP, 1.4 mm Form) Note: The control dimension is the millimeter column SYMBOL ...
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REV. 1.0.0 REVISION HISTORY D R ATE EVISION August 2007 Rev P1.0.0 Preliminary Datasheet. March 2008 Rev 1.0.0 Final Datasheet. Updated DC and AC Electrical Characteristics. EXAR Corporation reserves the right to make changes to the products contained in this ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO 44 REV. 1.0.0 ...
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REV. 1.0.0 GENERAL DESCRIPTION................................................................................................ 1 F .................................................................................................................................................... 1 EATURES A .............................................................................................................................................. 1 PPLICATIONS F 1. XR16M554 B D IGURE LOCK IAGRAM IGURE IN UT SSIGNMENT IGURE IN ...
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XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO 4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 28 4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE................................................. 28 T 13: UART RESET CONDITIONS FOR CHANNELS A-D .................................................................................................. 29 ABLE ...