XR16L2751CM EXAR [Exar Corporation], XR16L2751CM Datasheet - Page 35

• Manufacturer Part Number: XR16L2751CM
• Description: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
• Manufacturer: EXAR [Exar Corporation]

XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
EMSR[5:4]: Extended RTS Hysteresis
EMSR[6]: LSR Interrupt Mode
EMSR[7]: 16X Sampling Rate Mode
Logic 0 = 8X Sampling Rate.
Logic 1 = 16X Sampling Rate (for 16C2550 compatibility, default).
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this is
not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 13
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
See MCR bit-7 and the baud rate table also.
This register contains the device ID (0x0A for XR16L2751). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.13
4.14
4.15
Logic 0 = LSR Interrupt Delayed (for 16C2550 compatibility, default). LSR bits 2, 3, and 4 will generate an
interrupt when the character with the error is in the RHR.
Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
Baud Rate = (Clock Frequency / 16) / Divisor
FIFO Level Register (FLVL) - Read-Only
Baud Rate Generator Registers (DLL and DLM) - Read/Write
Device Identification Register (DVID) - Read Only
for details.
EMSR
B
IT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
-5
EMSR
B
T
IT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ABLE
-4
14: A
FCTR
B
IT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
-1
UTO
35
RTS H
FCTR
B
IT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-0
YSTERESIS
RTS# H
(C
HARACTERS
±16
±24
±32
±40
±44
±48
±52
±12
±20
±28
±36
±4
±6
±8
±8
YSTERESIS
0
)
áç
áç
áç
áç