XR16L2751CM EXAR [Exar Corporation], XR16L2751CM Datasheet - Page 23
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XR16L2751CM
Manufacturer Part Number
XR16L2751CM
Description
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
Manufacturer
EXAR [Exar Corporation]
Datasheet
1.XR16L2751CM.pdf
(52 pages)
Available stocks
Company
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Manufacturer
Quantity
Price
Part Number:
XR16L2751CM
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
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Part Number:
XR16L2751CM-F
Manufacturer:
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Company:
Part Number:
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Manufacturer:
Exar Corporation
Quantity:
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Part Number:
XR16L2751CM-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Company:
Part Number:
XR16L2751CMTR-F
Manufacturer:
Exar Corporation
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XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
.
A
A2-A0
DDRESS
1 1 1
1 1 1
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
T
ABLE
EMSR
N
MCR
FLVL
RHR
MSR
THR
FCR
LCR
SPR
R
LSR
IER
ISR
AME
EG
9: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
R
W
WR
WR
WR
RD
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
CTS Int.
Enabled
Enable
Enable
Trigger
Global
FIFOs
Pres-
Mode
B
BRG
caler
Error
Input
Bit-7
Bit-7
CD#
Bit-7
Sam-
pling
Rate
Bit-7
16X
IT
0/
0/
-7
RX FIFO
Imd/Dly#
IR Mode
RTS Int.
Enabled
ENable
Enable
Trigger
Set TX
THR &
FIFOs
Empty
Break
B
Inter-
Input
Error
Bit-6
Bit-6
Bit-6
Bit-6
TSR
LSR
rupt.
RI#
IT
0/
0/
-6
16C550 Compatible Registers
TX FIFO
Set Par-
XonAny
Xoff Int.
Enable
Source
Trigger
Empty
DSR#
B
Hyst.
Input
Bit-5
Bit-5
Bit-5
THR
Bit-5
Auto
RTS
Bit-5
INT
bit-3
ity
IT
0/
0/
0/
0/
-5
23
TX FIFO
Lopback
Internal
Source
Enable
Trigger
Enable
Break
Sleep
Mode
Parity
CTS#
B
Even
Input
Hyst.
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Auto
RTS
bit-2
INT
RX
IT
0/
0/
0/
-4
S
HADED BITS ARE ENABLED WHEN
OP2#/INT
RX Fram-
Inversion
Stat. Int.
ing Error
Modem
Source
Enable
Enable
Enable
Enable
RS485
Output
Output
Mode
Parity
Delta
B
DMA
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
Auto
INT
IT
-3
RX Line
(OP1#)
Enable
Source
Reset
Rsrvd
Parity
Rsrvd
B
FIFO
Delta
Error
Bit-2
Bit-2
Stat.
Bit-2
Stop
Bit-2
Bit-2
INT
Bits
RI#
Int.
RX
TX
IT
-2
Source
Control
Enable
Length
Output
Empty
Reset
DSR#
Count
RTS#
Over-
B
Word
Delta
Rx/Tx
FIFO
Error
FIFO
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
bit-1
INT
run
RX
RX
TX
Int
IT
-1
EFR B
Source
Control
Enable
Enable
Length
Output
Ready
FIFOs
DTR#
Rx/Tx
Count
CTS#
B
Word
Delta
FIFO
Bit-0
Bit-0
Data
Bit-0
Bit-0
Data
Bit-0
Bit-0
bit-0
INT
RX
Int.
RX
áç
áç
áç
áç
IT
-0
IT
-4=1
FCTR[6]=0
FCTR[6]=1
C
LCR[7]=0
LCR[7]=0
LCR[7]=0
LCR[7]=0
OMMENT