XR88C92CJ EXAR [Exar Corporation], XR88C92CJ Datasheet - Page 15

• Manufacturer Part Number: XR88C92CJ
• Description: DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
• Manufacturer: EXAR [Exar Corporation]

1
A3 A2 A1 A0
Rev. 1.31
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
Register
[Default]
MRA0[00]
MRB0[00]
MRA1[00]
MRB1[00]
MRA2[00]
MRB2[00]
SRA[00]
SRB[00]
CSRA[00]
CSRB[00]
CRA[00]
CRB[00]
RXA[XX]
RXB[XX]
TXA[XX]
TXB[XX]
IPCR[00]
ACR[00]
ISR[00]
IMR[00]
CTPU[00]
CUR[00]
CTPL[00]
CLR[00]
GPR[00]
OPCR[00]
STCR[XX]
SOPR[00]
SPCR[XX]
ROPR[00]
IPR[XX]
command
Loopback
dog timer
Received
rate set
change
change
Watch
control
BIT-7
select
select
Bit-15
mode
break
Misc.
clock
Baud
Used
Delta
Input
Input
RTS
Bit-7
Bit-7
Bit-7
Bit-7
OP7
Bit-7
Bit-7
port
port
Not
IP3
RX
RX
X
X
command
Loopback
Framing
break B
break B
level [1]
level [0]
trigger
trigger
select
BIT-6
Bit-14
mode
clock
Misc.
mode
Delta
Delta
Delta
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
error
OP6
IP2
C/T
IP6
RX
RX
RX
X
X
command
level [1]
control
trigger
BIT-5
Parity
Bit-13
mode
Misc.
mode
ready
ready
clock
Delta
Error
Bit-5
Bit-5
Bit-5
Bit-5
RTS
error
RxB
Bit-5
OP5
Bit-5
RxB
IP1
C/T
IP5
RX
T X
T X
X
X
15
command
Overrun
level [0]
control
BIT-4
trigger
Parity
mode
Misc.
mode
ready
ready
Bit-12
clock
Delta
error
Bit-4
Bit-4
Bit-4
Bit-4
OP4
Bit-4
Bit-4
Auto
CTS
TxB
TxB
IP0
C/T
IP4
RX
T X
X
X
disable
length
empty
BIT-3
Parity
Bit-11
mode
clock
ready
ready
Delta
used
Bit-3
Bit-3
input
Bit-3
Bit-3
Bit-3
Bit-3
Stop
OP3
Not
IP3
IP3
C/T
C/T
IP3
int.
bit
Tx
T X
T X
X
X
XR88C92/192
break A
break A
enable
length
BIT-2
ext. 2
Parity
ready
Bit-10
Baud
clock
Delta
Delta
Delta
Bit-2
Bit-2
input
Bit-2
Bit-2
Bit-2
type
Stop
Bit-2
OP3
rate
IP2
IP2
IP2
int.
bit
Tx
T X
T X
X
X
Rx FIFO
Factory
disable
length
length
BIT-1
mode
ready
ready
Word
clock
input
Delta
Stop
Bit-1
Bit-1
Bit-9
Bit-1
Bit-1
OP2
Bit-1
Bit-1
RxA
RxA
test
IP1
IP1
int.
IP1
full
RX
bit
T X
X
X
enable
length
length
BIT-0
ext. 1
Word
ready
clock
ready
ready
Baud
Delta
Bit-0
Bit-0
input
Bit-0
Bit-0
Bit-0
Bit-0
Stop
Bit-8
OP2
TxA
TxA
rate
IP0
IP0
IP0
int.
Rx
RX
bit
T X
X
X