XR88C92CJ EXAR [Exar Corporation], XR88C92CJ Datasheet
XR88C92CJ
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XR88C92CJ Summary of contents
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... Parity, framing, and over run error detection Programmable 16-bit timer/counter On-chip crystal oscillator Power down mode ORDERING INFORMATION Part number Package Operating temperature Device Status XR88C92CP 40-Lead PDIP 0° C XR88C92CJ 44-Lead PLCC 0° C XR88C92CV 44-Lead TQFP 0° C XR88C92IP 40-Lead PDIP -40° C XR88C92IJ 44-Lead PLCC -40° ...
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XR88C92/192 Package Description 40 Pin DIP Package - ...
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Block Diagram - Rev. 1.31 XR88C92/192 ...
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XR88C92/192 SYMBOL DESCRIPTION (* 44 pin TQFP) Symbol Pin 44 40 RXA, RXB 35,11 31,10 TXA, TXB 33,13 30,11 RESET 38 34 OP0 32 29 OP1 14 12 OP2 31 28 OP3 15 13 OP4 30 27 Rev. 1.31 Signal ...
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SYMBOL DESCRIPTION (* 44 pin TQFP) Symbol Pin 44 40 OP5 16 14 OP6 29 26 OP7 17 15 A0-A3 2,4, 1,3, 40,42, 6,7 5,6 XTAL1 36 32 XTAL2 37 33 GND 22 20 16,17 -INT 24 21 IP0 8 ...
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XR88C92/192 SYMBOL DESCRIPTION (* 44 pin TQFP) Symbol Pin 44 40 IP3 3 2 IP4 43 39 IP5 42 38 IP6 D0-D7 28,18 25,16 22,12 27,19 24,17 21,13 26,20 23,18 20,14 25,21 22,19 19,15 -IOW ...
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INTERNAL CONTROL LOGIC The internal control logic of the XR88C92/192 receives operation commands from the central processing unit (CPU) and generates appropriate signals to the internal sections to control device operation. The internal control logic takes in the following inputs: ...
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XR88C92/192 the parallel outputs OP3 through OP7 to provide dis- crete interrupt outputs for the transmitters, the receiv- ers, and the C/T. See 'Configuring Multi-purpose Out- puts' section for details. DATA BUS BUFFER (D0 - D7) The data bus buffer ...
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OP2 - OP7: The other outputs (OP2 - OP7) are configured via the OPCR. Please see the description under the OPCR register for the details. CRYSTAL INPUTS (XTAL1 & XTAL2 crystal is used connected between XTAL1 ...
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XR88C92/192 This is also reflected in the Interrupt Status Register, ISR bit-0 for channel A and bit-4 for channel B. This is different from the TxRDY bit in the status register. The TxRDY bit in the status register (SRA, SRB ...
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OR of these respective bits, for all the data bytes in the FIFO stack since the last reset error command (see CRA, CRB bits 7:4) was issued. That is, beginning immediately after ...
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XR88C92/192 station. When the slave stations' receivers detect an address character, each receiver notifies its respective CPU by setting receiver ready (-RXRDY) and generating an interrupt, if programmed to do so. Each slave station CPU then compares the received address ...
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Users can program the counter to generate an interrupt request for this condition on the -INT output by unmasking the bit-3 in the Interrupt Mask Register (IMR, address 0x5). After 0x0000 the count becomes 0xFFFF, and the counter continues counting ...
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XR88C92/192 address 0xE) is read, the C/T terminates the current countdown sequence and sets its output to a '1' (OP3 can be programmed to show this output). The C/T is then initialized to the pre-load value, and begins a new ...
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Register BIT-7 [Default MRA0[00] Watch MRB0[00] dog timer MRA1[00 MRB1[00] RTS control MRA2[00] Loopback 1 ...
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XR88C92/192 MODE REGISTER 0 (MR0A, MR0B) This register is accessed only when command is applied via CRA, CRB register (upper nibble = 0xB). After reading or writing to MR0A (or MR0B) register, the mode register pointer will point to MR1A ...
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Register) to reset the pointer to MR0 or MR1. MR2A, MR2B Bits 3-0: Stop bit length. 0000 = 0.563 (default) 1000 = 1.563 0001 = 0.625 1001 = 1.625 0010 = 0.688 1010 = 1.688 0011 = 0.750 1011 = ...
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XR88C92/192 Baud Rate Table for a 3.6864MHz clock. Data rates would double for a 7.3728MHz clock. MR0 Bits 2,0=0 CSRA, CSRB SET-1 Bits 7:4 or ACR Bits 3:0 Bit-7=0 0000 (default) 50 0001 110 0010 134.5 0011 200 0100 300 ...
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Start Break. Forces the transmitter output to go low and stay low. If transmitter is empty the start of the break condition will be de- layed up to two bit times. If transmitter is active, ...
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XR88C92/192 following table shows how to select the clock source for the C/T when used in counter mode or timer mode. ACR C/T Clock Source Bits 6:4 Mode Counter External (IP2 Counter TXAClk1-Transmit A ...
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If the corresponding bit in this register is a zero, the state of the bit in the interrupt status register has no effect on the -INT ...
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XR88C92/192 START COUNTER/TIMER REGISTER (STCR) Read Only Reading from this register will start the C/T. Data values returned should be ignored. STOP COUNTER/TIMER REGISTER (SPCR) - Read Only Reading from this register will stop the C/T. Data values returned should ...
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PROGRAMMING EXAMPLES The following examples show how to initialize the XR88C92/192 for various operating conditions: A) The first example will initialize channel XR88C92 device for regular RX/TX. The operating parameters will be 9600 baud, 8 word length, ...
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XR88C92/192 ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation DC ELECTRICAL CHARACTERISTICS FOR XR88C92 AND XR88C192 T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% ...
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AC ELECTRICAL CHARACTERISTICS T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter T T Clock pulse duration 1w Oscillator/Clock frequency 3w T Address Valid ...
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XR88C92/192 - - rite ) Figure 3: Bus Timing (Read/Write cycle) IP6-IP0 T9s -IOR ...
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ENABLE -RxRDY -FFULL -RxRDY/ -FFULL -IOR Status Data (D1) OVERRUN ERROR -RTS ENABLE -TxRDY -IOW -CTS -RTS Rev. 1. D11 Will be lost due to overrun Figure 6: Receive Timing Break ...
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XR88C92/192 -IOW -IOR -INT ExCLK Rev. 1.31 T11d T11d Figure 8: Interrupt Timing T1w T2w T3w Figure 9: External clock Timing 28 XR92-NT XR92-CK ...
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ating P lane ote ontrol dim ens ion is the ...
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XR88C92/192 ote ontrol dimens ion is the ...
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XR88C92/192 EXPLANATION OF DATA SHEET REVISIONS: FROM TO 1.20 1.30 Added and updated Device Status to front page. Added 5V tolerant input descriptions. Clarified Programming example D. Clarified SRA, SRB Bit-2 description. 1.30 1.31 Clarified that 5V tolerant inputs are ...