AK4371VN AKM [Asahi Kasei Microsystems], AK4371VN Datasheet - Page 43

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AK4371VN

Manufacturer Part Number
AK4371VN
Description
DAC with built-in PLL & HP-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

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6) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → MOUT
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
(2) PMVCM bit should be changed to “1” after PDN pin goes “H”.
(3) LIN1M, LIN2M, LIN3M, RIN1M, RIN2M and RIN3M bits should be changed to “1” after PMVCM bit is changed
(4) When LIN1M, LIN2M, LIN3M, RIN1M, RIN2M or RIN3M bit is changed to “1”, LIN1, RIN1, LIN2, RIN2, LIN3
(5) PMMO bit should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2μF) after LIN1M,
(6) When the PMMO bit is changed, pop noise is output from MOUT pins.
MS0596-E-00
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be
stopped when DAC is not used.
to “1”.
or RIN3 pin is biased to 0.475 x AVDD.
LIN2M, LIN3M, RIN1M, RIN2M or RIN3M bits are changed to “1”.
PMMO bit
Power Supply
PDN pin
PMVCM bit
LIN1M, RIN1M,
LIN2M, RIN2M,
LIN3M, RIN3M bits
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
MMUTE,
ATTM3-0 bits
MOUT pin
Figure 34. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 and MOUT
10H(MUTE)
(1) >150ns
(Hi-Z)
(Hi-Z)
(2) >0s
(4)
(3) >0s
(5) >2ms
(6)
0FH(0dB)
- 43 -
(6)
Don’t care
(Hi-Z)
(Hi-Z)
(5) >2ms
(6)
[AK4371]
2007/04

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