ATA5423_06 ATMEL [ATMEL Corporation], ATA5423_06 Datasheet - Page 91

• Manufacturer Part Number: ATA5423_06
• Description: UHF ASK/FSK Transceiver
• Manufacturer: ATMEL [ATMEL Corporation]

16. Digital Timing Characteristics
All parameters refer to GND and are valid for T
application (6V)) and V
4841C–WIRE–05/06
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
12.1
12.2
13.1
13.2
13.3
13.4
13.5
No.
12
13
Parameters
Basic Clock Cycle of the Digital Circuitry
Basic clock cycle
Extended basic clock
cycle
RX Mode/RX Polling Mode
Sleep time
Start
Start
processing
Time for bit check
Bit
-
rate range
-
-
up PLL RX mode from IDLE mode
up signal
VS2
= 5.0V (Base
Test Conditions
XLIM = 0
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
XLIM = 1
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
Sleep and XSleep are
defined in control
register 4
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
Average time during
polling. No RF signal
applied.
f
Signal data rate
Manchester
(Lim_min and Lim_max
up to ±50% of t
Figure 9-4 on page
Bit
input signal f
N
N
N
N
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Signal
Bit-check
Bit-check
Bit-check
Bit-check
-
check time for a valid
-
= 1/(2 × t
station Application(5V)) unless otherwise specified.
= 0
= 3
= 6
= 9
amb
Signal
ee
= 25°C. V
ee
)
, see
56)
VS1
Pin
= V
S2
= 3.0V (1 Li battery application (3V)), V
T
Startup_Sig_Proc
BR_Range
T
T
Symbol
Startup_PLL
T
T
T
Bit_check
XDCLK
DCLK
Sleep
× T
× T
Sleep ×
× T
X
1024 ×
16/f
3/f
6/f
9/f
T
Min.
Sleep
882
498
306
210
1.0
2.0
4.0
8.0
DCLK
16
Signal
Signal
Signal
8
4
2
1
8
4
2
DCLK
DCLK
DCLK
XTO
×
798.5 ×
1/f
T
Typ.
ATA5423/25/28/29
DCLK
Signal
3.5/f
6.5/f
9.5/f
Sleep ×
× T
× T
798.5 ×
× T
X
1024 ×
16/f
T
T
Max.
Sleep
VS2
10.0
20.0
882
498
306
210
2.5
5.0
DCLK
DCLK
16
8
4
2
1
8
4
2
DCLK
DCLK
DCLK
Signal
Signal
Signal
XTO
= 6.0V (2 Li battery
×
Kbit/s
Unit
ms
ms
µs
µs
µs
Type*
C
A
A
A
A
A
A
91