M40Z300MH1F STMICROELECTRONICS [STMicroelectronics], M40Z300MH1F Datasheet - Page 10

• Manufacturer Part Number: M40Z300MH1F
• Description: 5 V or 3 V NVRAM supervisor for up to 8 LPSRAMs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Operation
2.1
Note:
2.2
10/25
Two to four decode
The M40Z300/W includes a 2 input (A, B) decoder which allows the control of up to 4
independent SRAMs. The truth table for these inputs is shown in
Table 2.
Figure 6.
During system design, compliance with the SRAM timing parameters must comprehend the
propagation delay between E1
Data retention lifetime calculation
Most low power SRAMs on the market today can be used with the M40Z300/W NVRAM
SUPERVISOR. There are, however some criteria which should be used in making the final
choice of which SRAM to use. The SRAM must be designed in a way where the chip enable
input disables all other inputs to the SRAM. This allows inputs to the M40Z300/W and
SRAMs to be “Don't Care” once V
guarantee data retention down to V
sufficient to meet the system needs with the chip enable propagation delays included. If the
SRAM includes a second chip enable pin (E2), this pin should be tied to V
If data retention lifetime is a critical parameter for the system, it is important to review the
data retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0 V. Manufacturers generally specify a typical condition
for room temperature along with a worst case condition (generally at elevated
temperatures). The system level requirements will determine the choice of which value to
use.
E
H
L
L
L
L
A, B
E
E1 CON - E4 CON
Truth table
Address-decode time
Inputs
B
H
H
X
L
L
CON
Doc ID 5679 Rev 5
A
X
H
H
L
L
CC
tAS
- E4
CC
falls below V
= 2.0 V. The chip enable access time must be
CON
E1
.
H
H
H
H
CON
L
tEDL
PFD
(min). The SRAM should also
E2
H
H
H
H
CON
L
Outputs
tEDH
Table
E3
M40Z300, M40Z300W
2.
H
H
H
H
CON
L
OUT
.
E4
H
H
H
H
CON
L
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