M40Z300MH STMICROELECTRONICS [STMicroelectronics], M40Z300MH Datasheet - Page 3

• Manufacturer Part Number: M40Z300MH
• Description: NVRAM CONTROLLER for up to EIGHT LPSRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Table 2. Absolute Maximum Ratings
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
OPERATION
The M40Z300/W, as shown in Figure 4, can con-
trol up to four (eight, if placed in parallel) standard
low-power SRAMs. These SRAMs must be config-
ured to have the chip enable input disable all other
input signals. Most slow, low-power SRAMs are
configured like this, however many fast SRAMs
are not. During normal operating conditions, the
conditioned chip enable (E1
pins follow the chip enable (E) input pin with timing
shown in Table 7. An internal switch connects V
to
This switch has a voltage drop of less than 0.3V
(I
When V
E1
of E. In this situation, the SRAM is unconditionally
write protected as V
ance threshold (V
er fail detection value associated with V
selected by the Threshold Select (THS) pin and is
shown in Table 6A. For the M40Z300W, the THS
pin selects both the supply voltage and V
shown in Table 6B.
Note: In either case, THS pin must be connected
to either V
OUT1
CON
Symbol
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
T
V
).
V
P
T
STG
I
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
CC
to E4
O
IO
A
D
CC
SS
CON
degrades during a power failure,
or V
Ambient Operating Temperature
Storage Temperature (V
Input or Output Voltages
Supply Voltage
Output Current
Power Dissipation
OUT
PFD
are forced inactive independent
CC
). For the M40Z300 the pow-
.
falls below an out-of-toler-
CON
to E4
CON
Parameter
CC
(1)
Off)
) output
PFD
PFD
V
OUT
CC
as
is
.
SNAPHAT
SOIC
M40Z300
M40Z300W
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time t
E1
write protecting the SRAM. A power failure during
a write cycle may corrupt data at the currently ad-
dressed location, but does not jeopardize the rest
of the SRAM’s contents. At voltages below V
(min), the user can be assured the memory will be
write protected within the Write Protect Time
(t
Table 7).
As V
disconnects V
to V
(V
age V
I
When V
back to the supply voltage. Outputs E1
E4
mum) after the power supply has reached V
independent of the E input, to allow for processor
stabilization (see Figure 6).
OUT2
WPT
SO
CON
CON
OUT
). Below the V
CC
) provided the V
(see Table 6A/6B).
OHB
to E4
are held inactive for t
continues to degrade, the internal switch
. This occurs at the switchover voltage
CC
to the SRAM and can supply current
rises above V
CON
CC
and connects the internal battery
are unconditionally driven high,
–0.3 to V
SO
–55 to 125
–0.3 to 4.6
–40 to 85
CC
, the battery provides a volt-
–0.3 to 7
0 to 70
Value
M40Z300, M40Z300W
20
fall time exceeds t
1
CC
SO
+0.3
, V
CER
OUT
(120ms maxi-
is switched
Unit
mA
°C
°C
W
V
V
CON
F
(See
WPT
PFD
3/16
PFD
to
,
,