X4043 INTERSIL [Intersil Corporation], X4043 Datasheet - Page 9

• Manufacturer Part Number: X4043
• Description: CPU Supervisor with 4kbit EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

The state of the control register can be read at any time
by performing a random read at address 1FFh, using
the special preamble. Only one byte is read by each
register read operation. The X4043/45 resets itself after
the first byte is read. The master should supply a stop
condition to be consistent with the bus protocol, but a
stop is not required to end this operation.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next opera-
tion immediately after the stop condition.
BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
The block protect bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to one of eight
segments of the array.
0
0
0
0
1
1
1
1
7
0
0
0
1
1
0
0
1
1
WD1 WD0
6
0
1
0
1
0
1
0
1
Protected Addresses
000h - 1FFh
180h - 1FFh
100h - 1FFh
000h - 07Fh
None (factory setting)
000h - 00Fh
000h - 01Fh
000h - 03Fh
5
BP1
(Size)
4
(128 bytes
(256 bytes
(512 bytes)
(128 bytes)
(16 bytes)
(32 bytes)
(64 bytes)
9
BP0
3
)
)
RWEL
2
Upper 1/2 (Q3,Q4)
First 2 pgs (P2)
First 4 pgs (P4)
First 8 pgs (P8)
Upper 1/4 (Q4)
First Page (P1)
Full Array (All)
Array Lock
WEL
None
1
BP2
X4043, X4045
0
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
watchdog timer. The options are shown below.
Writing to the Control Register
Changing any of the nonvolatile bits of the control reg-
ister requires the following steps:
– Write a 02H to the control register to set the write
– Write a 06H to the control register to set both the
– Write a value to the control register that has all the
– A read operation occurring between any of the previ-
– The RWEL bit cannot be reset without writing to the
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the control register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.
WD1
enable latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
register write enable latch (RWEL) and the WEL bit.
This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
control bits set to the desired state. This can be rep-
resented as 0xys t01r in binary, where xy are the
WD bits, and rst are the BP bits. (Operation pre-
ceeded by a start and ended with a stop). Since this
is a nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the non-
volatile bits again. If bit 2 is set to ‘1’ in this third step
(0xys t11r) then the RWEL bit is set, but the WD1,
WD0, BP2, BP1 and BP0 bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
ous operations will not interrupt the register write
operation.
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
0
0
1
1
WD0
0
1
0
1
Watchdog Time Out Period
Disabled (factory setting)
600 milliseconds
200 milliseconds
1.4 seconds
September 30, 2005
FN8118.1