X4043 INTERSIL [Intersil Corporation], X4043 Datasheet - Page 11

• Manufacturer Part Number: X4043
• Description: CPU Supervisor with 4kbit EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

Figure 8. Acknowledge Response From Receiver
X4043/45 ADDRESSING
Slave Address Byte
Following a start condition, the master must output a
slave address byte. This byte consists of several parts:
– a device type identifier that is ‘1010’ to access the
– two bits of ‘0’.
– one bit that becomes the MSB of the address.
– one bit of the slave command byte is a R/W bit. The
– After loading the entire slave address byte from the
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.
Slave Address Byte
Figure 9. X4043/45 Addressing
Array
Control Reg.
array and ‘1011’ to access the control register.
R/W bit of the slave address byte defines the opera-
tion to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 8.
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
from Receiver
Slave Byte
Word Address
Data Output
Data Output
Transmitter
1
1
A7
SCL from
Master
from
0
0
A6
1
1
A5
11
Start
0
1
A4
0
A3
0
A2
1
A1
A8 R/W
X4043, X4045
A0
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
– SDA pin is the input mode.
– RESET signal is active for t
SERIAL WRITE OPERATIONS
Byte Write
For a write operation, the device requires the slave
address byte and a word address byte. This gives the
master access to any one of the words in the array.
After receipt of the word address byte, the device
responds with an acknowledge, and awaits the next
eight bits of data. After receiving the 8 bits of the data
byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating a
stop condition, at which time the device begins the inter-
nal write cycle to the nonvolatile memory. During this
internal write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 10.
A write to a protected block of memory will suppress
the acknowledge bit.
ble to write to the device.
8
Acknowledge
9
PURST
.
September 30, 2005
FN8118.1