TSC87C52-12CAB TEMIC [TEMIC Semiconductors], TSC87C52-12CAB Datasheet - Page 9

• Manufacturer Part Number: TSC87C52-12CAB
• Description: CMOS 0 to 33 MHz Programmable 8-bit Microcontroller
• Manufacturer: TEMIC [TEMIC Semiconductors]

MATRA MHS
Rev. C – 10 Sept 1997
The reset value of SCON is 0000 0000b.
Timer 2
The Timer 2 in the TSC87C52 operates identically to the Timer 2 in the 80C52 but includes the following
enhancements. For a complete understanding of the TSC87C52 Timer 2 please refer to the description in the 80C51
Hardware Description Guide.
Auto–reload (up or down counter)
Enhanced Timer 2 can now be programmed to count up or down when configured in its 16–bit auto–reload mode. This
feature is controlled by the DCEN (Down Counter Enable) bit. DCEN is located in T2MOD at bit location 0 (see
Table 5). Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 6. In this mode the T2EX pin
controls the direction of count.
A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at FFFFh and set the TF2 bit. This overflow also
causes the 16–bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. Now the timer underflows when TH2 and TL2 equal the values stored
in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes FFFFh to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows. In this operating mode, EXF2 does not flag an
interrupt.
Symbol
REN
TB8
RB8
RI
OSC
TI
T2
12
Description
Serial Reception Enable bit
Ninth bit to transmit in mode 2 and 3
Ninth bit received in mode 2 and 3
Transmit Interrupt Flag
Receive Interrupt Flag
Figure 6 Timer 2 Auto–Reload Mode Up/Down Counter
Set to enable serial reception.
Clear to disable serial reception.
Set to transmit a logic 1 in the 9th bit.
Clear to transmit a logic 0 in the 9th bit.
Set by hardware if 9th bit received is logic 1.
Clear by hardware if 9th bit received is logic 0.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 4 and Figure 5 in the other modes.
Clear to acknowledge interrupt.
C/T2
TR2
Preliminary
(DOWN COUNTING RELOAD VALUE)
(UP COUNTING RELOAD VALUE)
RCAP2L
(8–bit)
(8–bit)
(8–bit)
TL2
FFh
RCAP2H
(8–bit)
(8–bit)
(8–bit)
TH2
FFh
T2EX
COUNT DIRECTION
1= UP
0= DOWN
TOGGLE
TSC87C52
TF2
EXF2
INTERRUPT
TIMER 2
9