EP7312-IB-90 CIRRUS [Cirrus Logic], EP7312-IB-90 Datasheet - Page 14
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EP7312-IB-90
Manufacturer Part Number
EP7312-IB-90
Description
High-performance, Low-power, System-on-chip with SDRAM & Enhanced with SDRAM & Enhanced
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
1.EP7312-IB-90.pdf
(64 pages)
- Current page: 14 of 64
- Download datasheet (2Mb)
EP7312
High-Performance, Low-Power System on Chip
14
CI/O
IDD
at 74 MHz
IDD
at 90 MHz
VDD
IDD
IDD
IDD
Symbol
@ 25 C
@ 70 C
@ 85 C
idle
IDLE
a.
b.
c.
STANDBY
STANDBY
STANDBY
STANDBY
Note:
Transceiver capacitance
Standby current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Standby current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Standby current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Idle current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Idle current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Standby supply voltage
1) Total power consumption = IDD
2) A typical design will provide 3.3 V to the I/O supply (i.e., V
2) Pull-up current = 50 µA typical at V
Refer to the strength column in the pin assignment tables for all package types.
Assumes buffer has no pull-up or pull-down resistors.
The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.
compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).
Parameter
1
1
1
1
1
CORE
©
DD
Min
Copyright Cirrus Logic, Inc. 2005
2.0
x 2.5 V + IDD
8
-
-
-
-
-
-
-
-
-
-
= 3.3 V.
(All Rights Reserved)
IO
Typ
77
41
10
11
6
7
x 3.3 V
-
-
-
-
-
-
DDIO
), and 2.5 V to the remaining logic. This is to allow the I/O to be
Max
1693
10.0
570
111
163
-
-
-
-
-
-
-
Unit
mA
mA
µA
µA
µA
pF
V
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = V
VIL = GND ± 0.1 V
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = V
VIL = GND ± 0.1 V
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = V
VIL = GND ± 0.1 V
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = V
= GND ± 0.1 V
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = V
= GND ± 0.1 V
Minimum standby voltage for
state retention, internal SRAM
cache, and RTC operation only
DD
DD
DD
Conditions
± 0.1 V,
± 0.1 V,
± 0.1 V,
DD
DD
± 0.1 V, VIL
± 0.1 V, VIL
DS508F1
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