M38867E8AHP MITSUBISHI [Mitsubishi Electric Semiconductor], M38867E8AHP Datasheet - Page 33

• Manufacturer Part Number: M38867E8AHP
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER??
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Data Setup (PWM0)
The PWM0 output pin also functions as port P3
PWM0 output pin is selected from either P3
P5
0034
The PWM0 output becomes enabled state by setting bit 6 of the
port control register 1 (address 002E
of output data are set in the PWM0H register (address 0030
and the low-order six bits are set in the PWM0L register (address
0031
PWM1 is set as the same way.
PWM Operation
The 14-bit PWM data is divided into the low-order six bits and the
high-order eight bits in the PWM latch.
The high-order eight bits of data determine how long an “H”-level
signal is output during each sub-period. There are 64 sub-periods
in each period, and each sub-period is 256
signal is “H” for a length equal to N times , where
Table 7 Relationship between low-order 6 bits of data and
Fig. 30 PWM timing
Low-order 6 bits of data (PWML)
6
/PWM
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 0 0
0 0 1 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
16
16
).
).
period set by the ADD bit
01
P u l s e w i d t h m o d u l a t i o n r e g i s t e r H
P u l s e w i d t h m o d u l a t i o n r e g i s t e r L
S u b - p e r i o d s w h e r e “ H ” p u l s e w i d t h i s 1 6 . 0 s :
S u b - p e r i o d s w h e r e “ H ” p u l s e w i d t h i s 1 5 . 7 5 s :
1 5 . 7 5 s
by bit 4 of the AD/DA control register (address
LSB
6 4 s
m = 0
None
m=32
m=16, 48
m=8, 24, 40, 56
m=4, 12, 20, 28, 36, 44, 52, 60
m=2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m=1, 3, 5, 7, ................................................ ,57, 59, 61, 63
Sub-periods tm Lengthened (m=0 to 63)
1 5 . 7 5 s
16
). The high-order eight bits
1 5 . 7 5 s
:
:
(64 s) long. The
6 4 s
0
0
m = 7
or P5
/PWM
is the mini-
0 0 1 1 1 1 1 1
0 0 0 1 0 1
6
1 6 . 0 s
. The
00
16
or
)
4 0 9 6 s
6 4 s
m = 8
mum resolution (250 ns).
“H” or “L” of the bit in the ADD part shown in Figure 30 is added to
this “H” duration by the contents of the low-order 6-bit data accord-
ing to the rule in Table 7.
That is, only in the sub-period tm shown by Table 7 in the PWM
cycle period T = 64t, its “H” duration is lengthened to the minimum
resolution added to the length of other periods.
For example, if the high-order eight bits of the 14-bit data are 03
and the low-order six bits are 05
put in sub-periods t
Time at the “H” level of each sub-period almost becomes equal,
because the time becomes length set in the high-order 8 bits or
becomes the value plus , and this sub-period t (= 64 s, approxi-
mate 15.6 kHz) becomes cycle period approximately.
Transfer From Register to Latch
Data written to the PWML register is transferred to the PWM latch
at each PWM period (every 4096 s), and data written to the
PWMH register is transferred to the PWM latch at each sub-period
(every 64 s). The signal which is output to the PWM output pin is
corresponding to the contents of this latch. When the PWML regis-
ter is read, the latch contents are read. However, bit 7 of the
PWML register indicates whether the transfer to the PWM latch is
completed; the transfer is completed when bit 7 is “0” and it is not
done when bit 7 is “1.”
1 5 . 7 5 s
in all other sub-periods.
m = 8 , 2 4 , 3 2 , 4 0 , 5 6
m = a l l o t h e r v a l u e s
6 4 s
m = 9
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1 5 . 7 5 s
8
, t
MITSUBISHI MICROCOMPUTERS
24
, t
32
, t
40
1 5 . 7 5 s
16
, and t
, the length of the “H”-level out-
6 4 s
56
m = 6 3
3886 Group
is 4 , and its length is 3
33
16