M38867E8AHP MITSUBISHI [Mitsubishi Electric Semiconductor], M38867E8AHP Datasheet - Page 43

• Manufacturer Part Number: M38867E8AHP
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER??
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

[I
The I
cation format.
•Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. The I
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
bit (bit 7 of address 0016
BC2 are returned to “000
Also when a START condition is received, these bits become
“000
8 bits.
•Bit 3: I
This bit enables to use the multi-master I
this bit is set to “0,” the use disable status is provided, so that the
S
“1,” use of the interface is enabled.
When ES0 = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I
• Writing data to the I
•Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses.
When this bit is set to “0,” the addressing format is selected, so
that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or
when a general call (refer to “(5) I
ceived, transfer processing can be performed. When this bit is set
to “1,” the free data format is selected, so that slave addresses are
not recognized.
•Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit
is set to “0,” the 7-bit addressing format is selected. In this case,
only the high-order 7 bits (slave address) of the I
ter (address 0013
bit is set to “1,” the 10-bit addressing format is selected, and all
the bits of the I
data.
•Bit 6: System clock stop selection bit (CLKSTP)
When executing the WIT or STP instruction, this bit selects the
condition of system clock provided to the multi-master I
terface. When this bit is set to “0,” system clock and operation of
the multi-master I
STP instruction.
When this bit is set to “1,” system clock and operation of the multi-
master I
instruction is executed.
When the system clock stop selection bit is “1,” do not execute the
STP instruction.
•Bit 7: I
This bit selects the input level of the S
master I
status register at address 0014
abled.
DA
2
C Control Register (S1D)] 0015
2
and the S
2
” and the address data is always transmitted and received in
C control register (address 0015
2
2
2
C interface enable bit (ES0)
C-BUS interface pin input level selection bit
C-BUS interface.
2
C-BUS interface do not stop even when the WIT
CL
2
C address register are compared with address
become high-impedance. When the bit is set to
2
2
16
C-BUS interface stop by executing the WIT or
C interrupt request signal occurs immediately
) are compared with address data. When this
2
C data shift register (address 0012
2
16
”.
)) have been transferred, and BC0 to
16
2
).
C Status Register,” bit 1) is re-
CL
16
and S
) controls data communi-
2
C BUS interface. When
DA
16
2
C address regis-
pins of the multi-
2
C-BUS in-
16
) is dis
2
C
Fig. 38 Structure of I
T I S S C L K
b7
S T P
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1 0 B I T
S A D
A L S E S 0 B C 2 B C 1 B C 0
MITSUBISHI MICROCOMPUTERS
2
C control register
b 0
I
( S 1 D : a d d r e s s 0 0 1 5
A d d r e s s i n g f o r m a t
s e l e c t i o n b i t
B i t c o u n t e r ( N u m b e r o f
t r a n s m i t / r e c e i v e b i t s )
I
e n a b l e b i t
D a t a f o r m a t s e l e c t i o n b i t
S y s t e m c l o c k s t o p
s e l e c t i o n b i t
I
l e v e l s e l e c t i o n b i t
2
2
2
C c o n t r o l r e g i s t e r
C - B U S i n t e r f a c e
b 2 b 1 b 0
C - B U S i n t e r f a c e p i n i n p u t
3886 Group
0
0
0
0
1
1
1
1
0 : D i s a b l e d
1 : E n a b l e d
0 : A d d r e s s i n g f o r m a t
1 : F r e e d a t a f o r m a t
0 : S y s t e m c l o c k s t o p
1 : N o t s y s t e m c l o c k
0 : C M O S i n p u t
1 : S M B U S i n p u t
0 : 7 - b i t a d d r e s s i n g
f o r m a t
1 : 1 0 - b i t
a d d r e s s i n g f o r m a t
w h e n e x e c u t i n g W I T
o r S T P i n s t r u c t i o n
s t o p w h e n e x e c u t i n g
W I T i n s t r u c t i o n
( D o n o t u s e t h e S T P
i n s t r u c t i o n . )
0
0
1
1
0
0
1
1
0 : 8
1 : 7
0 : 6
1 : 5
0 : 4
1 : 3
0 : 2
1 : 1
1 6
)
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