M3850 RENESAS [Renesas Technology Corp], M3850 Datasheet - Page 22

• Manufacturer Part Number: M3850
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Manufacturer: RENESAS [Renesas Technology Corp]

3850 Group (Spec.A)
TIMERS
The 3850 group (spec. A) has four timers: timer X, timer Y, timer 1,
and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “00
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Fig. 17 Structure of timer XY mode register
Fig. 18 Structure of timer count source selection register
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The out-
put of prescaler 12 is counted by timer 1 and timer 2, and a timer
underflow sets the interrupt request bit.
Rev.2.10
REJ03B0093-0210
b 7
b 7
2005.11.14
page 22 of 86
b 0
b 0
T i m e r c o u n t s o u r c e s e l e c t i o n r e g i s t e r
( T C S S : a d d r e s s 0 0 2 8
T i m e r X c o u n t s o u r c e s e l e c t i o n b i t
0 : f ( X
1 : f ( X
T i m e r Y c o u n t s o u r c e s e l e c t i o n b i t
0 : f ( X
1 : f ( X
T i m e r 1 2 c o u n t s o u r c e s e l e c t i o n b i t
0 : f ( X
1 : f ( X
N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d )
b1b0
b5b4
Timer XY mode register
(TM : address 0023
T i m e r X o p e r a t i n g m o d e b i t
0 0 : T i m e r m o d e
0 1 : P u l s e o u t p u t m o d e
1 0 : E v e n t c o u n t e r m o d e
1 1 : P u l s e w i d t h m e a s u r e m e n t m o d e
T i m e r X c o u n t s t o p b i t
Timer Y operating mode bits
CNTR
T i m e r Y c o u n t s t o p b i t
C N T R
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
0 : C o u n t s t a r t
1: Interrupt at rising edge
0 : C o u n t s t a r t
1 : C o u n t s t o p
I N
I N
I N
I N
I N
C I N
0 : I n t e r r u p t a t f a l l i n g e d g e
1 : I n t e r r u p t a t r i s i n g e d g e
1 : C o u n t s t o p
0: Interrupt at falling edge
) / 1 6 ( f ( X
) / 2 ( f ( X
) / 1 6 ( f ( X
) / 2 ( f ( X
) / 1 6 ( f ( X
C o u n t a t r i s i n g e d g e i n e v e n t
C o u n t a t f a l l i n g e d g e i n e v e n t
Count at rising edge in event
Count at falling edge in event
c o u n t e r m o d e
c o u n t e r m o d e
counter mode
counter mode
)
0
1
a c t i v e e d g e s e l e c t i o n b i t
active edge selection bit
C I N
C I N
C I N
C I N
C I N
) / 2 a t l o w - s p e e d m o d e )
) / 2 a t l o w - s p e e d m o d e )
) / 1 6 a t l o w - s p e e d m o d e )
) / 1 6 a t l o w - s p e e d m o d e )
) / 1 6 a t l o w - s p e e d m o d e )
1 6
)
16
)
16
”, an un-
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source
selection bit.
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source
selection bit. Whenever the contents of the timer reach “00
signal output from the CNTR
CNTR
at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P2
put mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR
CNTR
When the CNTR
rising edge of the CNTR
When the CNTR
falling edge of the CNTR
(4) Pulse Width Measurement Mode
If the CNTR
counts the selected signals by the count source selection bit while
the CNTR
tive edge selection bit is “1”, the timer counts it while the CNTR
(or CNTR
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer underflows.
When switching the count source by the timer 12, X and Y count
source bits, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count input
signals.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
When timer X/timer Y underflow while executing the instruction
which sets “1” to the timer X/timer Y count stop bits, the timer X/
timer Y interrupt request bits are set to “1”. Timer X/Timer Y in-
terrupts are received if these interrupts are enabled at this time.
The timing which interrupt is accepted has a case after the in-
struction which sets “1” to the count stop bit, and a case after
the next instruction according to the timing of the timer under-
flow. When this interrupt is unnecessary, set “0” (disabled) to the
interrupt enable bit and then set “1” to the count stop bit.
Note
0
1
pin.
(or CNTR
1
0
) pin is at “L”.
(or CNTR
0
(or CNTR
0
0
1
(or CNTR
) active edge selection bit is “0”, output begins
(or CNTR
1
) pin is at “H”. If the CNTR
1
0
) active edge selection bit is “0”, the timer
0
(or CNTR
7
(or CNTR
( or port P4
1
1
) active edge selection bit is “0”, the
) active edge selection bit is “1”, the
0
(or CNTR
1
) pin is counted.
1
) pin is counted.
0
) direction register to out-
1
) pin is inverted. If the
0
(or CNTR
16
1
”, the
) ac-
0
or
0