COP8TAB5CMW8 NSC [National Semiconductor], COP8TAB5CMW8 Datasheet - Page 40

• Manufacturer Part Number: COP8TAB5CMW8
• Description: 8-Bit CMOS ROM Microcontroller with 2k or 4k Memory
• Manufacturer: NSC [National Semiconductor]

www.national.com
17.0 Memory Map
B9
BA
BB
BC
BD
BE to BF
C0 to C6
C7
C8
C9
CA
CB to CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0 to E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0 to FB
ADD REG
Address
ACB Status Register (ACBST)
ACB Control And Status (ACBCST)
ACB Control Register 1 (ACBCTL1)
ACB Own Address Register (ACBADDR)
ACB Control Register 2(ACBCTL2)
Reserved
Reserved
WATCHDOG Service Register
(Reg:WDSVR)
Port L MIWU Edge Select Register
(Reg:LWKEDG)
Port L MIWU Enable Register
(Reg:LWKEN)
Port L MIWU Pending Register
(Reg:LWKPND)
Reserved
Idle Timer Control Register (ITMR)
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Reserved
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved
Port J Data Register
Port J Configuration Register
Port J Input Pins (Read Only)
CPU Clock Prescale Register (CLKPS)
Reserved
Timer T1 Autoload Register T1RB Lower
Byte
Timer T1 Autoload Register T1RB Upper
Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1RA Lower
Byte
Timer T1 Autoload Register T1RA Upper
Byte
CNTRL Control Register
PSW Register
On-Chip RAM Mapped as Registers
(Continued)
Contents
40
Note: Reading memory locations 70H–7FH will return all ones. Reading
18.0 Instruction Set
18.1 INTRODUCTION
This section defines the instruction set of the COP8 Family
members. It contains information about the instruction set
features, addressing modes and types.
18.2 INSTRUCTION FEATURES
The strength of the instruction set is based on the following
features:
• Mostly single-byte opcode instructions minimize program
• One instruction cycle for the majority of single-byte in-
• Many single-byte, multiple function instructions such as
• Three memory mapped pointers: two for register indirect
• Sixteen memory mapped registers that allow an opti-
• Ability to set, reset, and test any individual bit in data
• Register-Indirect LOAD and EXCHANGE instructions
• Unique instructions to optimize program size and
18.3 ADDRESSING MODES
The instruction set offers a variety of methods for specifying
memory addresses. Each method is called an addressing
mode. These modes are classified into two categories: op-
erand addressing modes and transfer-of-control addressing
modes. Operand addressing modes are the various meth-
ods of specifying an address for accessing (reading or writ-
ing) data. Transfer-of-control addressing modes are used in
conjunction with jump instructions to control the execution
sequence of the software program.
18.3.1 Operand Addressing Modes
The operand of an instruction specifies what memory loca-
tion is to be affected by that instruction. Several different
operand addressing modes are available, allowing memory
locations to be specified in a variety of ways. An instruction
can specify an address directly by supplying the specific
address, or indirectly by specifying a register pointer. The
contents of the register (or in some cases, two registers)
FC
FD
FE
FF
ADD REG
size.
structions to minimize program execution time.
DRSZ.
addressing, and one for the software stack.
mized implementation of certain instructions.
memory address space, including the memory-mapped
I/O ports and registers.
with optional automatic post-incrementing or decrement-
ing of the register pointer. This allows for greater effi-
ciency (both in cycle time and program code) in loading,
walking across and processing fields in data memory.
throughput efficiency. Some of these instructions are:
DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.
Address
unused memory locations 80H–83H, 87H–93H will return undefined
data.
X Register
SP Register
B Register
On-Chip RAM Mapped as Register
Contents