COP8TAB5CMW8 NSC [National Semiconductor], COP8TAB5CMW8 Datasheet - Page 13
COP8TAB5CMW8
Manufacturer Part Number
COP8TAB5CMW8
Description
8-Bit CMOS ROM Microcontroller with 2k or 4k Memory
Manufacturer
NSC [National Semiconductor]
Datasheet
1.COP8TAB5CMW8.pdf
(54 pages)
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9.0 Pin Descriptions
L3 Multi-Input Wake-Up
L2 Multi-Input Wake-Up (optional 1.8V compatible input)
L1 Multi-Input Wake-Up or ACCESS.Bus Serial Clock (op-
L0 Multi-Input Wake-Up or ACCESS.Bus Serial Data (op-
FIGURE 7. I/O Port Configurations — Output Mode
tional 1.8V compatible input)
tional 1.8V compatible input)
FIGURE 8. I/O Port Configurations — Input Mode
FIGURE 6. I/O Port Configurations
(Continued)
20091761
20091762
20091760
13
10.0 Functional Description
The architecture of the device is a modified Harvard archi-
tecture. With the Harvard architecture, the program memory
(ROM) is separate from the data store memory (RAM). Both
Program Memory and Data Memory have their own separate
addressing space with separate address buses. The archi-
tecture, though based on the Harvard architecture, permits
transfer of data from ROM Memory to RAM.
10.1 CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t
C
) cycle time.
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