M306V0ME-107FP MITSUBISHI [Mitsubishi Electric Semiconductor], M306V0ME-107FP Datasheet - Page 43
M306V0ME-107FP
Manufacturer Part Number
M306V0ME-107FP
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Manufacturer
MITSUBISHI [Mitsubishi Electric Semiconductor]
Datasheet
1.M306V0ME-107FP.pdf
(256 pages)
- Current page: 43 of 256
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Rev. 1.0
Table 2.5.4 Operating modes dictated by settings of system clock control registers 0 and 1
2.5.7 Status Transition of BCLK
Invalid
Invalid
Invalid
CM17
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
internal clock . Table 2.5.4 shows the operating modes corresponding to the settings of system clock
control registers 0 and 1.
After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock division
select bit 0 (bit 6 at address 0006
clock .
Note: When switching the count source for BCLK between X
(1) Division by 2 mode
(2) Division by 4 mode
(3) Division by 8 mode
(4) Division by 16 mode
(5) No-division mode
(6) Low-speed mode
(7) Low power dissipation mode
0
1
1
0
The main clock is divided by 2 to obtain the BCLK.
The main clock is divided by 4 to obtain the BCLK.
The main clock is divided by 8 to obtain the BCLK. Note that oscillation of the main clock must have
stabilized before transferring from this mode to another mode.
The main clock is divided by 16 to obtain the BCLK.
The main clock is used as the BCLK.
fC is used as the BCLK. Note that oscillation of both the main and sub clocks must have stabilized
before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after
the sub clock starts. Therefore, the program must be written to wait until this clock has stabilized
immediately after powering up and after stop mode is cancelled.
f
C
is the BCLK and the main clock is stopped.
switched count source is sufficiently stable. Shift after taking the oscillation stabilizing time by
software.
Invalid
Invalid
Invalid
CM16
1
0
1
0
CM07
0
0
0
0
0
1
1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
16
) is set to “1”. The following shows the operational modes of internal
Invalid
Invalid
CM06
0
0
1
0
0
CM05
0
0
0
0
0
0
1
IN
Invalid
Invalid
Invalid
Invalid
Invalid
CM04
and X
1
1
and ON-SCREEN DISPLAY CONTROLLER
CIN
MITSUBISHI MICROCOMPUTERS
it needs that the oscillation of the
Division by 2 mode
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
Low-speed mode
Low power dissipation mode
M306V0ME-XXXFP
Operating mode of BCLK
M306V0EEFP
43
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