COP8SBE9 NSC [National Semiconductor], COP8SBE9 Datasheet
COP8SBE9
Related parts for COP8SBE9
COP8SBE9 Summary of contents
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... COP8SBE9/SCE9/SDE9 8-Bit CMOS Flash Microcontroller with 8k Memory, Virtual EEPROM and Brownout Reset General Description The COP8SBE9/SCE9/SDE9 Flash microcontrollers are highly integrated COP8 ™ Feature core devices, with 8k Flash memory and advanced features including Virtual EE- PROM, High Speed Timers, USART, and Brownout Reset. ...
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Block Diagram Ordering Information COP8 SB Family and Feature Set Indicator SB = Low Brownout Voltage SC = High Brownout Voltage Brownout www.national.com Part Numbering Scheme Program Program Memory Memory No. Of Pins Size ...
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Connection Diagrams Top View Plastic Chip Package See NS Package Number V44A Top View LLP Package See NS Package Number LQA44A 20032764 TSSOP Package See NS Package Number MTD48 20032755 3 20032759 Top View www.national.com ...
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Port Type Alt. Function L0 I/O MIWU or Low Speed OSC In L1 I/O MIWU or CKX or Low Speed OSC Out L2 I/O MIWU or TDX L3 I/O MIWU or RDX L4 I/O MIWU or T2A L5 I/O MIWU ...
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... General Description 1.1 EMI REDUCTION The COP8SBE9/SCE9/SDE9 devices incorporate circuitry that guards against electromagnetic interference - an in- creasing problem in today’s microcontroller board designs. National’s patented EMI reduction technology offers low EMI clock circuitry, gradual turn-on output drivers (GTOs) and internal Icc smoothing filters, to help circumvent many of the EMI issues influencing embedded control designs. National has achieved 15 dB– ...
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General Description examples. In many cases, the instruction set can simulta- neously execute as many as three functions with the same single-byte instruction. JID: (Jump Indirect); Single byte instruction decodes exter- nal events and jumps to corresponding service routines ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin Total Current into V Pin (Source) CC 2.0 Electrical Characteristics ...
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Electrical Characteristics TABLE 1. DC Electrical Characteristics (0˚C Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Output Current Levels B0-B3 Outputs Source (Weak Pull-Up Mode) Source (Push-Pull Mode) (Note 7) Sink (Push-Pull Mode) (Note ...
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AC Electrical Characteristics (0˚C Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer 1 Input High Time Timer 1 Input Low Time Timer 2 ...
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Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Operating Voltage Power Supply Rise Time Power Supply Ripple (Note 2) Supply Current (Note 3) High Speed Mode CKI = 10 MHz CKI = 3.33 MHz Dual ...
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DC Electrical Characteristics (−40˚C Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter RAM Retention Voltage, V (in HALT Mode) R Input Capacitance Voltage Force Execution from Boot ROM(Note 8) G6 Rise Time ...
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FIGURE 1. MICROWIRE/PLUS Timing 12 20032705 ...
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Pin Descriptions The COP8SBE/SCE/SDE I/O structure enables designers to reconfigure the microcontroller’s I/O functions with a single instruction. Each individual I/O pin can be independently configured as output pin low, output high, input with high impedance or input with ...
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Pin Descriptions L7 Multi-Input Wake-up L6 Multi-Input Wake-up L5 Multi-Input Wake-up or T2B (Timer T2B Input) L4 Multi-input Wake-up or T2A (Timer T2A Input) L3 Multi-Input Wake-up and/or RDX (USART Receive) L2 Multi-Input Wake-up or TDX (USART Transmit) L1 ...
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... SP points to the next available loca- tion on the stack. Program Flash Memory Device Memory Size (Flash) COP8SBE9 COP8SCE9 8192 COP8SDE9 4.3 DATA MEMORY The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration, Data and ...
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Functional Description segment (containing the 16 memory registers, I/O registers, control registers, etc.) is always available regardless of the contents of the S register, since the upper base segment (address range 0080 to 00FF) is independent of data seg- ...
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... Example: The following sets a value in the Option Register and User Identification for a COP8SBE9HVA7. The Option Register bit values shown select options: Security disabled, WATCHDOG enabled HALT mode enabled and execution will commence from Flash Memory. .chip 8SBE ...
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Functional Description ISPADLO: CLEARED ISPADHI: CLEARED PGMTIM: PRESET TO VALUE FOR 10 MHz CKI WATCHDOG (if enabled): The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, with the WATCHDOG service window ...
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Functional Description Timer starts counting the 240 to 256 t C soon as the V rises above the trigger voltage (approxi- CC mately 1.8V). This behavior is shown in Figure Case 1, V rises from 0V ...
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Functional Description High Speed Oscillator 20032715 TABLE 3. Crystal Oscillator Configuration 25˚ (pF Chip Chip Chip 18–36 ...
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Functional Description in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3) T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge EXPND External interrupt pending BUSY MICROWIRE/PLUS busy shifting flag EXEN ...
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In-System Programming (Continued) power-up executing from Boot ROM. When FLEX = 0, this assumes that either the MICROWIRE/PLUS ISP routine or external programming is being used to program the device. If using the MICROWIRE/PLUS ISP routine, the software in ...
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In-System Programming TABLE 9. PGMTIM Register Format (Continued ...
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In-System Programming (Continued) memory and reprogram it. If the device is subsequently reset before the Flex bit has been erased by specific Page Erase or Mass Erase ISP commands, execution will start from location 0000 in the Flash program ...
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In-System Programming TABLE 11. MICROWIRE/PLUS ISP Commands (Continued) Command Function MASS_ERASE Mass Erase READ_BYTE Read Byte BLOCKR Block Read WRITE_BYTE Write Byte BLOCKW Block Write EXIT EXIT INVALID N/A Note: The user must ensure that Block Writes do not ...
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In-System Programming Command/ Command Function Label Entry Point cpgerase Page Erase 0x17 cmserase Mass Erase 0x1A creadbf Read Byte 0x11 cblockr Block Read 0x26 cwritebf Write Byte 0x14 cblockw Block Write 0x23 exit EXIT 0x62 uwisp MICROWIRE/ 0x00 PLUS ...
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In-System Programming Register Name ISPADHI High byte of Flash Memory Address ISPADLO Low byte of Flash Memory Address ISPWR The user must store the byte to be written into this register before jumping into the write byte routine. ISPRD ...
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Timers The device contains a very versatile set of timers (T0, T1 and T2). Timers T1 and T2 and associated autoreload/capture registers power up containing random data. 6.1 TIMER T0 (IDLE TIMER) The device supports applications that require maintaining ...
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Timers (Continued) RSVD: This bit is reserved and must be set to 0. ITSEL2:0: Selects the Idle Timer period as described in Table 15, Idle Timer Window Length. Any time the IDLE Timer period is changed there is the ...
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Timers (Continued) In this mode the input pin TxB can be used as an indepen- dent positive edge sensitive interrupt input if the TxENB control flag is set. The occurrence of a positive edge on the TxB input pin ...
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Timers (Continued) lematic. Since any of these six registers or the PWM outputs can change as many as ten times in a single instruction cycle, performing an SBIT or RBIT operation with the timer running can produce unpredictable results. ...
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Power Saving Features 7.1 POWER SAVE MODE CONTROL REGISTER The ITMR control register allows for navigation between the three different modes of operation also used for the Idle Timer. The register bit assignments are shown below. This ...
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Power Saving Features 7.2 OSCILLATOR STABILIZATION Both the high speed oscillator and low speed oscillator have a startup delay associated with them. When switching be- tween the modes, the software must ensure that the appro- priate oscillator is started ...
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Power Saving Features 7.3.2 High Speed Idle Mode In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with the HALT mode. However, the high speed oscillator, IDLE Timer (Timer T0), ...
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Power Saving Features 3. Software clears the CCKSEL bit to 0. 7.4.1 Dual Clock HALT Mode The fully static architecture of this device allows the state of the microcontroller to be frozen. This is accomplished by stopping the high ...
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Power Saving Features bit T0PND, which is set on the same occurrence. The Idle Timer interrupt is enabled by setting bit T0EN in the ICNTRL register. Any time the IDLE Timer window length is changed there is the possibility ...
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Power Saving Features should be a NOP which should follow the enter IDLE instruc- tion.) The user must reset the IDLE Timer pending flag (T0PND) before entering the IDLE mode. As with the HALT mode, this device can also ...
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Power Saving Features to negative (high going low) for L Port bit 5, where bit 5 has previously been enabled for an input interrupt. The program would be as follows: RBIT 5, WKEN ; Disable MIWU SBIT 5, WKEDG ...
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USART (Continued) 8.1 USART CONTROL AND STATUS REGISTERS The operation of the USART is programmed through three registers: ENU, ENUR and ENUI. 8.2 DESCRIPTION OF USART REGISTER BITS ENU — USART CONTROL AND STATUS REGISTER (Ad- dress at 0BA) ...
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USART (Continued) XBIT9/PSEL0: Programs the ninth bit for transmission when the USART is operating with nine data bits per frame. For seven or eight data bits per frame, this bit in conjunction with PSEL1 selects parity. Read/Write, cleared on ...
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USART (Continued) 8.4 USART OPERATION The USART has two modes of operation: asynchronous mode and synchronous mode. 8.4.1 Asynchronous Mode This mode is selected by resetting the SSEL (in the ENUI register) bit to zero. The input frequency to ...
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USART (Continued) 8.6 USART INTERRUPTS The USART is capable of generating interrupts. Interrupts are generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two bytes of program memory space are reserved for each ...
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USART (Continued) many ways to calculate the two divisor factors, but one particularly effective method would be to achieve a 1.8432 MHz frequency coming out of the first stage. The 1.8432 MHz prescaler output is then used to drive ...
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USART (Continued) Using the above equation can be calculated first 2)/(16 x 19200) = 32.552 Now 32.552 is divided by each Prescaler Factor ( Table 19 ) ...
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Interrupts 9.1 INTRODUCTION The device supports eleven vectored interrupts. Interrupt sources include Timer 1, Timer 2, Timer T0, Port L Wake-up, Software Trap, MICROWIRE/PLUS, USART and External Input. All interrupts force a branch to location 00FF Hex in program ...
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Interrupts (Continued) An interrupt is an asychronous event which may occur be- fore, during, or after an instruction cycle. Any interrupt which occurs during the execution of an instruction is not acknowl- edged until the start of the next ...
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Interrupts (Continued) The default VIS interrupt vector can be useful for applica- tions in which time critical interrupts can occur during the servicing of another interrupt. Rather than restoring the pro- gram context ( etc.) and executing ...
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Interrupts (Continued) 9.4 NON-MASKABLE INTERRUPT 9.4.1 Pending Flag There is a pending flag bit associated with the non-maskable Software Trap interrupt, called STPND. This pending flag is not memory-mapped and cannot be accessed directly by the software. The pending ...
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Interrupts (Continued) user program should contain the Software Trap routine to perform a recovery procedure rather than a return to normal execution. Under normal conditions, the STPND flag is reset by a RPND instruction in the Software Trap service ...
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Interrupts (Continued) SERVICE: RBIT,EXPND,PSW . . . RET I 9.5 PORT L INTERRUPTS Port L provides the user with an additional eight fully select- able, edge sensitive interrupts which are all vectored into the same service subroutine. The interrupt ...
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WATCHDOG/CLOCK MONITOR TABLE 22. WATCHDOG Service Window Select WDSVR WDSVR Monitor Bit 7 Bit 10.1 CLOCK MONITOR The Clock Monitor aboard the device can be selected ...
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WATCHDOG/CLOCK MONITOR (Continued) 10.3 WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted: • Both the WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET. • Following RESET, the ...
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MICROWIRE/PLUS TABLE 24. MICROWIRE/PLUS Master Mode Clock Select SL1 SL0 Where t is the instruction cycle clock C 11.1 MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to ...
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MICROWIRE/PLUS clock. The SIO register is shifted on each falling edge of the SK clock. In the alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on the rising ...
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MICROWIRE/PLUS FIGURE 33. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High 12.0 Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address Contents S/ADD REG ...
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Memory Map (Continued) Address Contents S/ADD REG xxE0 Reserved xxE1 Flash Memory Write Timing Register (PGMTIM) xxE2 ISP Key Register (ISPKEY) xxE3 to xxE5 Reserved xxE6 Timer T1 Autoload Register T1RB Lower Byte xxE7 Timer T1 Autoload Register T1RB ...
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Instruction Set (Continued) fies which register serves as the pointer. Example: Exchange Memory with Accumulator, B Indirect X A,[B] Reg/Data Contents Memory Before Accumulator 01 Hex Memory Location 87 Hex 0005 Hex B Pointer 05 Hex Register B or ...
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Instruction Set (Continued) Contents Reg Before PCU 0C Hex PCL 77 Hex Jump Absolute Long. In this 3-byte instruction, 15 bits of the instruction opcode specify the new contents of the Pro- gram Counter. Example: Jump Absolute Long JMP ...
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Instruction Set (Continued) 13.4.8 Conditional Instructions The conditional instruction test a condition. If the condition is true, the next instruction is executed in the normal manner; if the condition is false, the next instruction is skipped. If Equal (IFEQ) ...
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Instruction Set (Continued) 13.6 INSTRUCTION SET SUMMARY ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical ...
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Instruction Set (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr. Jump SubRoutine JSRB Addr Jump SubRoutine Boot ROM JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No ...
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Instruction Set (Continued) Register [ (Note 17) 1 (Note 17) 1/1 LD B,Imm LD B,Imm LD Mem,Imm 2/2 LD Reg,Imm IFEQ MD,Imm > Note 17: = Memory location addressed directly. ...
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Nibble Lower 63 www.national.com ...
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Development Support IAR Embedded COP8-SW-EWCOP8 Workbench Tool EWCOP8-BL Set. Assembler-Only Version Hardware Emulation and Debug Tools Hardware COP8-EMFlash-00 Emulators COP8-DMFlash-00 COP8-IMFlash-00 Emulator Null COP8-EMFA-68N Target COP8-EMFA-28N Emulator Target COP8-EMFA-44P Package Adapters COP8-EMFA-68P NiceMon Debug COP8-SW-NMON Monitor Utility Development and ...
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... WCOP8 IDE and Emulator Debugger, with Assembler/ Linker/ CD-ROM Simulators/ Library Manager/ Compiler Demos/ Flash ISP and NiceMon Debugger Utilities/ Example Code/ etc. Includes all COP8 datasheets and documentation. Included with most tools from National. Unis Processor Processor Expert( from Unis Corporation - COP8 Code Generation and Simulation Expert tool with Graphical and Traditional user interfaces ...
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Development Support Hardware Tools for: Real-time Emulation; Target Hardware Debug; Target Design Test. Product COP8Flash COP8 In-Circuit Emulator for Flash Families. Windows based development and Emulators - real-time in-circuit emulation tool, with trace (EM=None; DM/IM=32k), s/w COP8-EMFlash breakpoints (DM=16, ...
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Development Support Vendor Home Office KANDA Systems Unit 17 -18 LTD. Glanyrafon Enterprise Park, Aberystwyth, Ceredigion, SY23 3JQ, UK Tel: +44 1970 621041 Fax: +44 1970 621040 K and K Kaergaardsvej 42 DK-8355 Development ApS Solbjerg Denmark Fax: +45-8692-8500 ...
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... Physical Dimensions inches (millimeters) unless otherwise noted Order Number COP8SBE9HLQ7, COP8SCE9HLQ7, COP8SDE9HLQ7, Order Number COP8SBE9IMT7, COP8SCE9IMT7, COP8SDE9IMT7, LLP Package (LQA) COP8SCE9HLQ9 or COP8SDE9HLQ9 NS Package Number LQA44A TSSOP Package (MTD) COP8SCE9IMT9 or COP8SDE9IMT9 NS Package Number MTD48 69 www.national.com ...
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... Physical Dimensions Order Number COP8SBE9HVA7, COP8SCE9HVA7, COP8SDE9HVA7, LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or ...