MCF5207 FREESCALE [Freescale Semiconductor, Inc], MCF5207 Datasheet - Page 37

• Manufacturer Part Number: MCF5207
• Description: Microprocessor Data Sheet
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

5.11.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN,
Table 17
The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
FEC_TXCLK frequency.
The transmit outputs (FEC_TXD[3:0], FEC_TXEN, FEC_TXER) can be programmed to transition from
either the rising or falling edge of FEC_TXCLK, and the timing is the same in either case. This options
allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Figure 25
5.11.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
Table 18
Figure 26
Freescale Semiconductor
Num
Num
M5
M6
M7
M8
M9
FEC_TXD[3:0] (outputs)
lists MII transmit channel timings.
lists MII asynchronous inputs signal timing.
shows MII transmit signal timings listed in
shows MII asynchronous input timings listed in
FEC_TXER, FEC_TXCLK)
FEC_TXCLK (input)
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER
invalid
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid
FEC_TXCLK pulse width high
FEC_TXCLK pulse width low
FEC_CRS, FEC_COL minimum pulse width
FEC_TXEN
FEC_TXER
MCF5208 ColdFire
Figure 25. MII Transmit Signal Timing Diagram
Characteristic
Characteristic
Table 18. MII Async Inputs Signal Timing
Table 17. MII Transmit Signal Timing
®
Microprocessor Data Sheet, Rev. 0.5
M5
Preliminary
M6
M7
Table
Table
17.
18.
35%
35%
Min
Min
1.5
—
M8
5
Preliminary Electrical Characteristics
Max
65%
65%
Max
25
—
—
FEC_TXCLK period
FEC_TXCLK period
FEC_TXCLK period
Unit
Unit
ns
ns
37