MCF51JF128VLH FREESCALE [Freescale Semiconductor, Inc], MCF51JF128VLH Datasheet - Page 32
MCF51JF128VLH
Manufacturer Part Number
MCF51JF128VLH
Description
MCF51JF128
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MCF51JF128VLH.pdf
(73 pages)
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Memories and memory interfaces
6.4.3 Mini-Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
32
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Num
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Description
Table 20. EzPort switching specifications (continued)
EP3
MCF51JF128 Data Sheet, Rev. 6, 01/2012.
EP5
Figure 6. EzPort Timing Diagram
EP6
EP7
EP4
EP8
EP9
EP2
Min.
0.0
0.0
0.0
15
15
—
—
Freescale Semiconductor, Inc.
Max.
25
12
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns