MC9S08QD2MPS FREESCALE [Freescale Semiconductor, Inc], MC9S08QD2MPS Datasheet - Page 39

• Manufacturer Part Number: MC9S08QD2MPS
• Description: 8-Bit HCS08 Central Processor Unit (CPU)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08QD4 series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct
page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.
Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated
to the highest address of the RAM in the Freescale Semiconductor-provided equate file).
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or through code executing from non-secure memory. See
description of the security feature.
4.5
The flash memory is intended primarily for program storage. In-circuit programming allows the operating
program to be loaded into the flash memory after final assembly of the application product. It is possible
to program the entire array through the single-wire background debug interface. Because no special
voltages are needed for flash erase and programming operations, in-application programming is also
possible through other software-controlled communication paths. For a more detailed discussion of
in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I,
Freescale Semiconductor document order number HCS08RMv1.
4.5.1
Features of the flash memory include:
4.5.2
Before any program or erase command can be accepted, the flash clock divider register (FCDIV) must be
written to set the internal clock for the flash module to a frequency (f
(see
normally this write is performed during reset initialization. FCDIV cannot be written if the access error
flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the
FCDIV register. One period of the resulting clock (1/f
Freescale Semiconductor
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Section 4.7.1, “Flash Clock Divider Register
Flash size
— MC9S08QD4/S9S08QD4: 4096 bytes (8 pages of 512 bytes each)
— MC9S08QD2/S9S08QD2: 2048 bytes (4 pages of 512 bytes each)
Single power supply program and erase
Command interface for fast program and erase operation
Up to 100,000 program/erase cycles at typical voltage and temperature
Flexible block protection
Security feature for flash and RAM
Auto power-down for low-frequency read accesses
Flash
Features
Program and Erase Times
LDHX
TXS
#RamLast+1
MC9S08QD4 Series MCU Data Sheet, Rev. 3
;point one past RAM
;SP<-(H:X-1)
(FCDIV).”) This register can be written only once, so
FCLK
) is used by the command processor to time
Section 4.6,
FCLK
Chapter 4 Memory Map and Register Definition
) between 150 kHz and 200 kHz
“Security,” for a detailed
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