ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 259
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ST7FMC1K2B3
Manufacturer Part Number
ST7FMC1K2B3
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST7FMC1K2B3.pdf
(309 pages)
- Current page: 259 of 309
- Download datasheet (6Mb)
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Figure 137. PLL And Clock Detector Signal Start Up Sequence
Notes:
1. Lock does not go low without resetting the PLLEN bit.
2. Before setting the CKSEL bit by software in order to switch to the PLL clock, a period of t
elapsed.
3. 2 clock cycles are missing after CKSEL = 1
4. CKSEL bit must be set before enabling the CSS interrupt (CSSIE=1).
CKSEL
OSCIN
PLLEN
(PLL and CKD)
PLL CLOCK
LOCK
f
CSSD
CSSIE
INTERRUPT
CLK
2)
4)
t
setup
t lock
OSCIN Clock
16Mhz
3)
PLL clock
f
VCO
t
hold
ST7MC1xx/ST7MC2xx
=
1)
6 Mhz
lock
must have
259/309
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