EP9312-EB CIRRUS [Cirrus Logic], EP9312-EB Datasheet - Page 31

• Manufacturer Part Number: EP9312-EB
• Description: Universal Platform System-on-chip Processor
• Manufacturer: CIRRUS [Cirrus Logic]

DS515PP7
ADDR valid
(Note 3,3-1)
(Note 3,3-2)
(Note 3,3-3)
DD (7:0)
DD (7:0)
DIORn/
(Note 1)
DIOWn
WRITE
IORDY
IORDY
IORDY
(Note 2)
(Note 2)
READ
Note:
1. Device address consists of signals IDECS0n, IDECS1n and IDEDA (2:0)
2. Data consists of DD (7:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is
to be extended is made by the host after t
are described in the following three cases:
3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before t
3-3 Device negates IORDY before t
and may be asserted for no more than t
before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated
and DIORn is asserted, the device shall place read data on DD (7:0) for t
t
1
©
Copyright 2005 Cirrus Logic (All Rights Reserved)
Figure 17. Register Transfer to/from Device
A
A
, but causes IORDY to be asserted before t
. IORDY is released prior to negation and may be asserted for no more than t
t
A
A
from the assertion of DIORn or DIOWn. The assertion and negation or IORDY
C
t
before release: no wait generated.
DDV
t
2
t
C
t
B
t
t
3
0
t
5
RD
t
RD
before asserting IORDY.
A
. IORDY is released prior to negation
Universal Platform SOC Processor
t
t
C
6
t
6z
t
9
t
4
t
2i
C
EP9312
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