LPC2157 NXP [NXP Semiconductors], LPC2157 Datasheet
LPC2157
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LPC2157 Summary of contents
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... LCD driver Rev. 01 — 15 October 2008 1. General description The LPC2157/2158 is a multi-chip module consisting of a LPC2138/2148 single-chip microcontroller combined with a PCF8576D Universal LCD driver in a low-cost 100-pin package. The LCD driver provides 32 segments and supports from backplanes. Display overhead is minimized by an on-chip display RAM with auto-increment addressing ...
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... NXP Semiconductors 4. Block diagram P0[31:28], P0[27:26] P0[25], P0[23:0] (1) LPC2157 only. Fig 1. LPC2157_2158_1 Product data sheet P1[31:25], P1[17:16] LPC2157/ LPC2158 (1) , MCU Block diagram of LPC2157/2158 Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers PCF8576D LCD CONTROLLER 002aad382 © NXP B.V. 2008. All rights reserved. S[31:0] BP[3:0] V LCD ...
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... AND 1 AD1[7:0] AOUT P0[31:28] and GENERAL P0[25:0] PURPOSE I/O P1[31:16] PWM[6:1] (1) Pins shared with GPIO. (2) USB DMA controller with RAM accessible as general purpose RAM and/or DMA is available in LPC2158 only. (3) LPC2157 only. Fig 2. Microcontroller section block diagram LPC2157_2158_1 Product data sheet (1) (1) TMS TDI (1) (1) ...
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... BLINKER DISPLAY CONTROLLER POWER- ON RESET COMMAND DECODER 2 I C-BUS CONTROLLER SA0 1 LPC2157FBD 25 Pin configuration for LPC2157 Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers S[31:0] DISPLAY SEGMENT OUTPUTS DISPLAY LATCH SHIFT REGISTER INPUT DISPLAY OUTPUT BANK RAM BANK SELECTOR 40 4 BITS ...
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... NXP Semiconductors Fig 5. 5.2 Pin description Table 2. Pin description LPC2157 Symbol Pin P0[0] to P0[31] [1] P0[0]/TXD0/ 7 PWM1 [2] P0[1]/RXD0/ 9 PWM3/EINT0 [3] P0[2]/SCL0/ 10 CAP0[0] [3] P0[3]/SDA0/ 14 MAT0[0]/EINT1 [4] P0[4]/SCK0/ 15 CAP0[1]/AD0[6] [4] P0[5]/MISO0/ 17 MAT0[1]/AD0[7] LPC2157_2158_1 Product data sheet 1 LPC2158FBD 25 Pin configuration for LPC2158 Type Description I/O Port 0: Port 32-bit I/O port with individual direction controls for each bit. ...
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... NXP Semiconductors Table 2. Pin description LPC2157 Symbol Pin [4] P0[6]/MOSI0/ 18 CAP0[2]/AD1[0] [2] P0[7]/SSEL0/ 19 PWM2/EINT2 [4] P0[8]/TXD1/ 20 PWM4/AD1[1] [2] P0[9]/RXD1/ 21 PWM6/EINT3 [4] P0[10]/RTS1/ 22 CAP1[0]/AD1[2] [3] P0[11]/CTS1/ 23 CAP1[1]/SCL1 [4] P0[12]/DSR1/ 24 MAT1[0]/AD1[3] [4] P0[13]/DTR1/ 25 MAT1[1]/AD1[4] [3] P0[14]/DCD1/ 26 EINT1/SDA1 LPC2157_2158_1 Product data sheet …continued Type Description I/O P0[6] — General purpose input/output digital pin (GPIO). ...
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... NXP Semiconductors Table 2. Pin description LPC2157 Symbol Pin [4] P0[15]/RI1/ 28 EINT2/AD1[5] [2] P0[16]/EINT0/ 29 MAT0[2]/CAP0[2] [1] P0[17]/CAP1[2]/ 30 SCK1/MAT1[2] [1] P0[18]/CAP1[3]/ 79 MISO1/MAT1[3] [1] P0[19]/MAT1[2]/ 80 MOSI1/CAP1[2] [2] P0[20]/MAT1[3]/ 81 SSEL1/EINT3 [4] P0[21]/PWM5/ 91 AD1[6]/CAP1[3] [4] P0[22]/AD1[7]/ 92 CAP0[0]/ MAT0[0] [1] P0[23] 84 [5] P0[25]/AD0[4]/ 97 AOUT [7] P0[26]/AD0[5] 98 LPC2157_2158_1 Product data sheet …continued Type Description I/O P0[15] — General purpose input/output digital pin (GPIO). ...
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... NXP Semiconductors Table 2. Pin description LPC2157 Symbol Pin [7] P0[27]/AD0[0]/ 99 CAP0[1]/MAT0[1] [4] P0[28]/AD0[1]/ 1 CAP0[2]/MAT0[2] [4] P0[29]/AD0[2]/ 2 CAP0[3]/MAT0[3] [4] P0[30]/AD0[3]/ 3 EINT3/CAP0[0] [6] P0[31] 5 P1[0] to P1[31] [6] P1[16] 4 [6] P1[17] 100 [6] P1[25]/EXTIN0 16 [6] P1[26]/RTCK 12 [6] P1[27]/TDO 90 [6] P1[28]/TDI 86 [6] P1[29]/TCK 82 [6] P1[30]/TMS 78 [6] P1[31]/TRST 8 LPC2157_2158_1 Product data sheet …continued ...
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... NXP Semiconductors Table 2. Pin description LPC2157 Symbol Pin [8] RESET 83 [9] XTAL1 88 [9] XTAL2 87 [9] RTCX1 93 [9] RTCX2 13, 32, SS 39, 40, 85 11, 27 DDA V 38 DD(LCD LCD VREF 89 VBAT 31 SDA_LCD 34 SCL_LCD 35 SYNC 36 CLK 37 BP0 to BP3 S31 ...
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... P0[8] — General purpose input/output digital pin (GPIO). O TXD1 — Transmitter output for UART1. O PWM4 — Pulse Width Modulator output 4. I AD1[1] — ADC 1, input 1. Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers 2 C-bus compliance). 2 C-bus compliance). © NXP B.V. 2008. All rights reserved ...
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... CAP1[2] — Capture input for Timer 1, channel 2. I/O SCK1 — Serial Clock for SSP. Clock output from master or input to slave. O MAT1[2] — Match output for Timer 1, channel 2. Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers 2 C-bus compliance) 2 C-bus compliance). © NXP B.V. 2008. All rights reserved. ...
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... MAT0[3] — Match output for Timer 0, channel 3. I/O P0[30] — General purpose input/output digital pin (GPIO). I AD0[3] — ADC 0, input 3. I EINT3 — External interrupt 3 input. I CAP0[0] — Capture input for Timer 0, channel 0. Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers © NXP B.V. 2008. All rights reserved ...
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... Input from the oscillator amplifier. I Output to the oscillator circuit and internal clock generator circuits. I Input to the RTC oscillator circuit. O Output from the RTC oscillator circuit. I Ground reference. Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers © NXP B.V. 2008. All rights reserved ...
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... CLK — external clock input/output O BP0 to BP3: LCD backplane outputs S31: LCD segment outputs. 2 C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers © NXP B.V. 2008. All rights reserved ...
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... The LPC2157/2158 flash memory provides a minimum of 400000 erase/write cycles and 20 years of data-retention. 6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2157/2158 provide 32 kB and static RAM. LPC2157_2158_1 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 01 — ...
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... In case of LPC2158 only SRAM block intended to be utilized mainly by the USB can also be used as a general purpose RAM for data storage and code storage and execution. 6.4 Memory map The LPC2157/2158 memory map incorporates several distinct regions, as shown in Figure 6. In addition, the CPU interrupt vectors may be remapped to allow them to reside in either fl ...
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... The value of the output register may be read back, as well as the current state of the port pins. LPC2157/2158 introduce accelerated GPIO functions over prior LPC2000 devices: • GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing. ...
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... All I/O default to inputs after reset. 6.8 10-bit ADC The LPC2157/2158 contain two single 10-bit successive approximation ADCs. While ADC0 has eight channels (six channels for LPC2158), ADC1 has eight channels. Therefore, the total number of available ADC inputs for LPC2157 is 16 and for LPC2158 is 14. 6.8.1 Features • ...
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... Double buffer implementation for bulk and isochronous endpoints. 6.11 UARTs The LPC2157/2158 each contain two UARTs. In addition to standard transmit and receive data lines, the UART1 also provides a full modem control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in LPC2157/2158 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz. In addition, auto-CTS/RTS fl ...
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... The I 6.13 SPI serial I/O controller The LPC2157/2158 each contain one SPI controller. The SPI is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer ...
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... Multiple pins can be selected to perform a single capture or match function, providing an application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them. The LPC2157/2158 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts ...
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... Pulse width modulator The PWM is based on the standard timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2157/2158. The timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events ...
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... Software must ‘release’ new match values before they can become effective. • May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit prescaler. LPC2157_2158_1 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 01 — 15 October 2008 LPC2157/2158 © NXP B.V. 2008. All rights reserved ...
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... PLL settling time is 100 s. 6.19.3 Reset and wake-up timer Reset has two sources on the LPC2157/2158: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fi ...
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... V detection to reliably interrupt regularly-executed event loop to sense the condition. 6.19.5 Code security This feature of the LPC2157/2158 allow an application to control whether it can be debugged or protected from observation. If after reset on-chip bootloader detects a valid checksum in flash and reads 0x8765 4321 from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be protected from observation ...
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... Idle mode. 6.20 Emulation and debugging The LPC2157/2158 supports emulation and debugging via a JTAG serial port. Debugging functions are multiplexed with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself ...
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... RealMonitor software programmed into the on-chip flash memory. 6.21 LCD driver 6.21.1 General description The LCD segment driver in the LPC2157/2158 can interface to most LCDs using low multiplex rates. It generates the drive signals for static or multiplexed LCDs containing up to four backplanes and segments. The LCD controller communicates to a host using the I LCD driver are available on the LPC2157/2158 providing system fl ...
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... RAM. LPC2157_2158_1 Product data sheet Single-chip 16-bit/32-bit microcontrollers /24. osc(ctrl)LCD 4-bit RAM which stores LCD data. There is a one-to-one Rev. 01 — 15 October 2008 LPC2157/2158 © NXP B.V. 2008. All rights reserved ...
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... C-bus slave receiver. In the LPC2157/2158 the hardware Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers Table 5. blinking off 0 1536 Hz at pin CLK. The oscillator setting the hardware subaddress = 0. SS © ...
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... C-bus slave addresses 2 The I C-bus slave address is 0111 0000. The LCD controller is a write-only device and will not respond to a read access. LPC2157_2158_1 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 01 — 15 October 2008 LPC2157/2158 © NXP B.V. 2008. All rights reserved ...
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... RTC on ADC related pins [ tolerant I/O pins; only valid when the V DD supply voltage is present [2][3] other I/O pins [4] per supply pin [4] per ground pin [5] based on package heat transfer, not device power consumption Rev. 01 — 15 October 2008 LPC2157/2158 Min Max Unit 0.5 +3.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +5.1 V 0.5 +6.0 V ...
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... 0 0 DDA < V < Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers [1] Min Typ Max [2] 3.0 3.3 3.6 3.0 3.3 3.6 [3] 2.0 3.3 3.6 2.5 3 100 [4][5][ 5.5 ...
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... PCLK disabled to RTCK in the PCONP register; RTC clock = 32 kHz (from RTCX pins 3.3 V amb i(VBAT) CCLK = 25 MHz CCLK = 60 MHz OLS Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers [1] Min Typ Max - 100 - ...
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... Conditions 0 V < V < 3 |(D includes V range 1 3 GND L steady state drive SoftConnect = ON drops below 1 grounded 5 and D . Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers [1] Min Typ Max 5.25 0 ...
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... See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 7. Figure Figure 7. Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers Min Typ ...
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... Product data sheet (2) (5) (4) (3) 1 LSB (ideal) 1018 (LSB ) IA ideal ). D ). Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers offset error E O (1) 1019 1020 1021 1022 1023 1024 V V DDA SSA 1 LSB = 1024 002aac046 © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors ADx[y] Fig 8. Suggested ADC interface - LPC2157/2158 ADx[y] pin LPC2157_2158_1 Product data sheet LPC2XXX 20 k SAMPLE Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers R vsi ADx[y] V EXT 002aad458 © NXP B.V. 2008. All rights reserved ...
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... Figure 10 see Figure must reject as EOP; see Figure 10 must accept as EOP; see Figure 10 over specified ranges DD Conditions Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers Min Typ Max 110 1.3 - 2.0 160 - 175 2 ...
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... PERIOD FDEOP V DD CONNECT soft-connect switch R1 1.5 k VBUS Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers t CHCX t CLCH T cy(clk) 002aaa907 = 200 mV) extended source EOP width: t receiver EOP width: t USB-B connector 002aad410 FEOPT , t EOPR1 EOPR2 002aab561 © ...
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... Fig 12. LPC2158 USB interface using the UP_LED function on pin 17 LPC2157_2158_1 Product data sheet Single-chip 16-bit/32-bit microcontrollers 1.5 k UP_LED VBUS Rev. 01 — 15 October 2008 LPC2157/2158 USB-B connector 002aad411 © NXP B.V. 2008. All rights reserved ...
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... scale (1) ( 0.27 0.20 14.1 14.1 16.25 16.25 0.5 0.17 0.09 13.9 13.9 15.75 15.75 REFERENCES JEDEC JEITA MS-026 Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers detail 0.75 1.15 1 0.2 0.08 0.08 0.45 0.85 EUROPEAN PROJECTION SOT407 (1) (1) ...
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... Joint Test Action Group Microcontroller Unit Phase-Locked Loop Power-On Reset Pulse Width Modulator Resistance-Capacitance Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 13. Revision history Table 12. Revision history Document ID Release date LPC2157_2158_1 20081015 LPC2157_2158_1 Product data sheet Single-chip 16-bit/32-bit microcontrollers Data sheet status Change notice Product data sheet - Rev. 01 — 15 October 2008 LPC2157/2158 Supersedes - © NXP B.V. 2008. All rights reserved ...
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... I C-bus — logo is a trademark of NXP B.V. GoodLink — trademark of NXP B.V. SoftConnect — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 15 October 2008 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: LPC2157_2158_1 All rights reserved. Date of release: 15 October 2008 ...