P80C32EBBB PHILIPS [NXP Semiconductors], P80C32EBBB Datasheet - Page 49

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P80C32EBBB

Manufacturer Part Number
P80C32EBBB
Description
CMOS single-chip 8-bit microcontrollers
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheets

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DC ELECTRICAL CHARACTERISTICS
T
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
3. Capacitive loading on ports 0 and 2 may cause the V
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
5. See Figures 21 through 24 for I
6. This value applies to T
7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
8. Under steady state (non-transient) conditions, I
9. ALE is tested to V
10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF
1996 Aug 16
amb
SYMBOL
SYMBOL
V
V
V
V
V
V
V
I
I
I
I
R
C
IL
TL
LI
CC
IL
IH
IH1
OL
OL1
OH
OH1
CMOS single-chip 8-bit microcontrollers
RST
IO
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
address bits are stabilizing.
maximum value when V
If I
test conditions.
(except EA it is 25pF).
= 0 C to +70 C or –40 C to +85 C, V
OL
Active Mode:
Idle Mode:
Maximum I
Maximum I
Maximum total I
exceeds the test condition, V
Input low voltage
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
Output low voltage, ports 1, 2, 3
Output low voltage, port 0, ALE, PSEN
Output high voltage, ports 1, 2, 3
Output high voltage (port 0 in external bus mode),
ALE
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
Input leakage current, port 0
Power supply current (see Figure 20):
Internal reset pull-down resistor
Pin capacitance
Active mode @ 16MHz
Idle mode @ 16MHz
Power-down mode
9
OL
OL
, PSEN
per port pin:
per 8-bit port:
OH1
OL
I
I
CC
CC
, except when ALE is off then V
3
amb
for all outputs:
IN
= 0.9
= 0.18
10
is approximately 2V.
= 0 C to +70 C. For T
(except EA)
PARAMETER
PARAMETER
CC
FREQ + 1.1;
FREQ +1.0; See Figure 20.
5
test conditions.
OL
5
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
CC
15mA (*NOTE: This is 85 C specification.)
26mA
71mA
8
= 5.0V 10%; V
3
OL
8, 7
amb
must be externally limited as follows:
= –40 C to +85 C, I
OH
OH
6
on ALE and PSEN to momentarily fall below the (V
is the voltage specification.
SS
= 0V
0.45 < V
T
19
4.5V < V
T
amb
amb
CONDITIONS
I
I
I
I
OH
OL
OL
V
V
V
OH
V
See note 4
See note 5
TL
V
V
= –40 to +85 C
CC
CC
CC
CC
IN
IN
= 0 to +70 C
TEST
TEST
= 1.6mA
= 3.2mA
= –3.2mA
IN
= –750 A.
= –30 A
= 0.4V
= 2.0V
= 4.5V
= 4.5V
= 4.5V
= 4.5V
CC
< V
< 5.5V
CC
2
2
– 0.3
OL
OL
0.2V
V
V
s of ALE and ports 1 and 3. The noise is due
can exceed these conditions provided that no
0.7V
CC
CC
–0.5
MIN
CC
–1
40
– 0.7
– 0.7
CC
+0.9
80C52/80C54/80C58
LIMITS
CC
TYP
–0.7) specification when the
3
1
0.2V
V
V
Product specification
CC
CC
MAX
–650
–50
225
0.4
0.4
16
50
75
15
CC
10
4
+0.5
+0.5
–0.1
UNIT
UNIT
mA
mA
k
pF
V
V
V
V
V
V
V
A
A
A
A
A

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