P87LPC762BDH PHILIPS [NXP Semiconductors], P87LPC762BDH Datasheet - Page 45

• Manufacturer Part Number: P87LPC762BDH
• Description: Low power, low price, low pin count 20 pin microcontroller with 2 kbyte OTP
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
2001 Oct 26
Low power, low price, low pin count (20 pin)
microcontroller with 2 kbyte OTP
WDCON
BIT
WDCON.7, 6
WDCON.5
WDCON.4
WDCON.3
WDCON.2–0 WDS2–0
R/C OSCILLATOR
Address: A7h
Not Bit Addressable
500 kHz
CLOCK OUT
WDCLK * WDTE
STATE CLOCK
ENABLE
SYMBOL
WDS2–0
WDRUN
WDOVF
WDCLK
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
—
—
7
FEED DETECT
WATCHDOG
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Watchdog timer overflow flag. Set when a watchdog reset or timer overflow occurs. Cleared when
the watchdog is fed.
Watchdog run control. The watchdog timer is started when WDRUN = 1 and stopped when
WDRUN = 0. This bit is forced to 1 (watchdog running) if the WDTE configuration bit = 1.
Watchdog clock select. The watchdog timer is clocked by CPU clock/6 when WDCLK = 1 and by
the watchdog RC oscillator when WDCLK = 0. This bit is forced to 0 (using the watchdog RC
oscillator) if the WDTE configuration bit = 1.
Watchdog rate select.
BOD (xxx.x)
POR (xxx.x)
Timeout Clocks
Reset Value:
—
6
1,048,576
131,072
262,144
524,288
WDTE + WDRUN
Figure 34. Watchdog Timer Control Register (WDCON)
16,384
32,768
65,536
8,192
Figure 33. Block Diagram of the Watchdog Timer
WDOVF
5
10h for other rest sources if the watchdog is enabled via the WDTE configuration bit.
00h for other reset sources if the watchdog is disabled via the WDTE configuration bit.
30h for a watchdog reset.
WDRUN
Minimum Time
4
165 ms
330 ms
660 ms
1.3 sec
(WDCON.2–0)
10 ms
20 ms
41 ms
82 ms
WDS2–0
WDCLK
42
CLEAR
3
20-BIT COUNTER
WDS2
8 TO 1 MUX
2
8 MSBs
Nominal Time
1.60 sec
3.20 sec
100 ms
200 ms
400 ms
800 ms
25 ms
50 ms
WDS1
1
WDS0
0
S
R
WDTE (UCFG1.7)
Maximum Time
Q
1280 ms
2.60 sec
5.30 sec
160 ms
320 ms
640 ms
40 ms
80 ms
(WDCON.5)
WDOVF
87LPC762
WATCHDOG
WATCHDOG
INTERRUPT
RESET
SU01182
Preliminary data
SU01476