P89LV51RD2BA PHILIPS [NXP Semiconductors], P89LV51RD2BA Datasheet - Page 29

• Manufacturer Part Number: P89LV51RD2BA
• Description: 8-bit 80C51 3 V low power 64 kB Flash microcontroller with 1 kB RAM
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 14342
Product data
7.3.1 Mode 0
7.3.2 Mode 1
Table 18:
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a fixed divide-by-32 prescaler.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls
over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is
enabled to the Timer when TRn =
GATE =
width measurements). TRn is a control bit in the Special Function Register TCON
(Figure
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper
3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn)
does not clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1 (see
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and
TLn) are used. See
Bit
3
2
1
0
Fig 8. Timer/Counter 0 or 1 in Mode 0 (13-bit counter).
INTn Pin
TnGate
Tn pin
Osc/6
TRn
7). The GATE bit is in the TMOD register.
1
allows the Timer to be controlled by external input INTn, to facilitate pulse
TCON - Timer/Counter control register (address 88H) bit description
Symbol
IE1
IT1
IE0
IT0
Rev. 04 — 02 December 2004
Figure
C/T = 0
C/T = 1
Description
Interrupt 1 Edge flag. Set by hardware when external interrupt 1
edge/low level is detected. Cleared by hardware when the interrupt
is processed, or by software.
Interrupt 1 Type control bit. Set/cleared by software to specify
falling edge/low level that triggers external interrupt 1.
Interrupt 0 Edge flag. Set by hardware when external interrupt 0
edge/low level is detected. Cleared by hardware when the interrupt
is processed, or by software.
Interrupt 0 Type control bit. Set/cleared by software to specify
falling edge/low level that triggers external interrupt 0.
9.
1
and either GATE = 0 or INTn =
P89LV51RB2/RC2/RD2
control
8-bit microcontrollers with 80C51 core
Figure 8
(5-bits)
TLn
shows Mode 0 operation.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
(8-bits)
THn
Figure
overflow
8). There are two
1
. (Setting
TFn
002aaa519
interrupt
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