P89LPC915 PHILIPS [NXP Semiconductors], P89LPC915 Datasheet - Page 30

• Manufacturer Part Number: P89LPC915
• Description: 8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V Flash with 8-bit A/D converter
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 14397
Product data
9.4 Watchdog oscillator option
9.5 External clock input option
9.6 CPU Clock (CCLK) wake-up delay
9.7 CPU Clock (CCLK) modification: DIVM register
The Watchdog has a separate oscillator which has a frequency of 400 kHz. This
oscillator can be used to save power when a high clock frequency is not needed.
In this configuration, the processor clock is derived from an external source driving
the CLKIN pin. The rate may be from 0 Hz up to 18 MHz. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until V
reached its specified level. When system power is removed V
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when V
specified operating voltage.
The P89LPC915/916/917 has an internal wake-up timer that delays the clock until it
stabilizes. The delay is 224 OSCCLK cycles plus 60 to 100 s.
The OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
Fig 10. Block diagram of oscillator control.
OSCILLATOR
(7.3728 MHz)
OSCILLATOR
CLKIN
WATCHDOG
(400 kHz)
RC
GENERATOR
BAUD RATE
Rev. 04 — 17 December 2004
RCCLK
8-bit microcontrollers with accelerated two-clock 80C51 core
UART
OSCCLK
XCLK
DIVM
TIMERS 1 & 0
PCLK
P89LPC915/916/917
peripheral clock
RCCLK
DD
falls below the minimum
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
I
2
2
C
RTCS1:0
CCLK
PCLK
(P89LPC916)
DD
SPI
ADC1/DAC1
will fall below
WDT
CPU
RTC
002aaa831
CLKOUT
DD
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has