AT91SAM9260-CU ATMEL [ATMEL Corporation], AT91SAM9260-CU Datasheet - Page 16

• Manufacturer Part Number: AT91SAM9260-CU
• Description: AT91 ARM Thumb Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

6.4
6.5
6.6
6.7
7. Processor and Architecture
7.1
16
PIO Controllers
I/O Line Drive Levels
Shutdown Logic Pins
Slow Clock Selection
ARM926EJ-S Processor
AT91SAM9260
All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor.
Refer to the section on DC Characteristics in “AT91SAM9260 Electrical Characteristics” for
more information. Programming of this pull-up resistor is performed independently for each I/O
line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals and that must be enabled as Peripheral
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing
tables.
The PIO lines are high-drive current capable. Each of these I/O lines can drive up to 16 mA per-
manently except PC4 to PC31 that are VDDIOM powered.
The SHDN pin is an output only, which is driven by the Shutdown Controller.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
The AT91SAM9260 slow clock can be generated either by an external 32,768 Hz crystal or the
on-chip RC oscillator.
Table 6-1
Table 6-1.
The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. The
32,768 Hz startup delay is 1200 ms whereas it is 240 µs for the internal RC oscillator (refer to
Table
device.
OSCSEL
0
1
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
• Two Instruction Sets
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
acceleration
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
– Instruction Fetch (F)
6-1). The pin OSCSEL must be tied either to GND or VDDBU for correct operation of the
defines the states for OSCSEL signal.
Slow Clock Selection
Slow Clock
Internal RC
External 32768 Hz
Startup Time
240 µs
1200 ms
6221IS–ATARM–12-Aug-08