AT32UC3L064-AUTES ATMEL [ATMEL Corporation], AT32UC3L064-AUTES Datasheet - Page 40

• Manufacturer Part Number: AT32UC3L064-AUTES
• Manufacturer: ATMEL [ATMEL Corporation]

6.1.4
6.1.4.1
6.1.4.2
6.2
6.2.1
6.2.2
32099DS–06/2010
Startup Considerations
Power-up Sequence
Starting of Clocks
Fetching of Initial Instructions
Maximum Rise Rate
Minimum Rise Rate
To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values
described in
Recommended order for power supplies is also described in this chapter.
The integrated Power-Reset circuitry monitoring the VDDIN powering supply requires a mini-
mum rise rate for the VDDIN power supply.
See
If the application can not ensure that the minimum rise rate condition for the VDDIN power sup-
ply is met, one of the following configuration can be used:
This chapter summarizes the boot sequence of the AT32UC3L. The behavior after power-up is
controlled by the Power Manager. For specific details, refer to the Power Manager chapter.
After power-up, the device will be held in a reset state by the Power-On Reset circuitry for a
short time to allow the power to stabilize throughout the device. After reset, the device will use
the System RC Oscillator (RCSYS) as clock source. Please refer to
the frequency for this oscillator.
On system start-up, the DFLL is disabled. All clocks to all modules are running. No clocks have
a divided frequency; all parts of the system receive a clock with the same frequency as the Sys-
tem RC Oscillator.
When powering up the device, there may be a delay before the voltage has stabilized, depend-
ing on the rise time of the supply used. The CPU can start executing code as soon as the supply
is above the POR threshold, and before the supply is stable. Before switching to a high-speed
clock source, the user should use the BOD to make sure the VDDCORE is above the minimum
level (1.62V).
After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset
address, which is 0x80000000. This address points to the first address in the internal Flash.
The code read from the internal Flash is free to configure the system to use for example the
DFLL, to divide the frequency of the clock routed to some of the peripherals, and to gate the
clocks to unused peripherals.
• A logic “0” value is applied during power-up on pin PA11 until VDDIN rises above 1.2V.
• A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V.
Table 7-3 on page 42
Table 7-3 on page
for the minimum rise rate value.
42.
AT32UC3L016/32/64
Table 7-17 on page 49
for
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