PIC24FJ32GB002-E/ML MICROCHIP [Microchip Technology], PIC24FJ32GB002-E/ML Datasheet - Page 225

• Manufacturer Part Number: PIC24FJ32GB002-E/ML
• Description: 28/44-Pin, 16-Bit, Flash Microcontrollers with USB On-The-Go (OTG) and nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 18-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY)
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/K-0, HS
Note:
STALLIF
U-0
—
Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause
all set bits at the moment of the write to become cleared.
Unimplemented: Read as ‘0’
STALLIF: STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the peripheral device during the handshake phase of the
0 = A STALL handshake has not been sent
ATTACHIF: Peripheral Attach Interrupt bit
1 = A peripheral attachment has been detected by the module; set if the bus state is not SE0 and there
0 = No peripheral attachment is detected
RESUMEIF: Resume Interrupt bit
1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for
0 = No K-state is observed
IDLEIF: Idle Detect Interrupt bit
1 = Idle condition is detected (constant Idle state of 3 ms or more)
0 = No Idle condition is detected
TRNIF: Token Processing Complete Interrupt bit
1 = Processing of current token is complete; read U1STAT register for endpoint information
0 = Processing of current token is not complete; clear U1STAT register or load next token from U1STAT
SOFIF: Start-of-Frame Token Interrupt bit
1 = A Start-of-Frame token is received by the peripheral or the Start-of-Frame threshold reached by
0 = No Start-of-Frame token is received or threshold reached
UERRIF: USB Error Condition Interrupt bit
1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set
0 = No unmasked error condition has occurred
DETACHIF: Detach Interrupt bit
1 = A peripheral detachment has been detected by the module; Reset state must be cleared before
0 = No peripheral detachment detected. Individual bits can only be cleared by writing a ‘1’ to the bit
ATTACHIF
R/K-0, HS
transaction in Device mode
has been no bus activity for 2.5 s
full speed)
this bit
U-0
the host
this bit can be reasserted
position as part of a word write operation on the entire register. Using Boolean instructions or bit-
wise operations to write to a single bit position will cause all set bits at the moment of the write to
become cleared.
—
U = Unimplemented bit, read as ‘0’
K = Write ‘1’ to clear bit
‘1’ = Bit is set
RESUMEIF
R/K-0, HS
U-0
—
R/K-0, HS
IDLEIF
U-0
PIC24FJ64GB004 FAMILY
—
HS = Hardware Settable bit
‘0’ = Bit is cleared
R/K-0, HS
TRNIF
U-0
—
R/K-0, HS
SOFIF
U-0
—
x = Bit is unknown
UERRIF
U-0
R-0
—
DS39940D-page 225
DETACHIF
R/K-0, HS
U-0
—
bit 8
bit 0