PIC24FJ32GB002-E/ML MICROCHIP [Microchip Technology], PIC24FJ32GB002-E/ML Datasheet - Page 186

• Manufacturer Part Number: PIC24FJ32GB002-E/ML
• Description: 28/44-Pin, 16-Bit, Flash Microcontrollers with USB On-The-Go (OTG) and nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC24FJ64GB004 FAMILY
REGISTER 16-2:
DS39940D-page 186
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
ACKSTAT
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC
R-0, HSC R-0, HSC
IWCOL
ACKSTAT: Acknowledge Status bit
1 = NACK was detected last
0 = ACK was detected last
Hardware set or clear at the end of Acknowledge.
TRSTAT: Transmit Status bit
(When operating as I
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at the beginning of master transmission. Hardware clear at the end of slave Acknowledge.
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches the general call address. Hardware clear at the Stop detection.
ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at the match of the 2nd byte of matched 10-bit address. Hardware clear at the Stop detection.
IWCOL: Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register was still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D/A: Data/Address bit (when operating as I
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was the device address
Hardware clear occurs at device address match. Hardware set after a transmission finishes or at reception
of the slave byte.
TRSTAT
I2COV
I2CxSTAT: I2Cx STATUS REGISTER
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U-0
D/A
—
2
C master. Applicable to master transmit operation.)
U-0
—
P
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/C-0, HSC
U-0
—
S
2
C slave)
R/C-0, HS
R-0, HSC
BCL
R/W
HSC = Hardware Settable/Clearable bit
x = Bit is unknown
2
C module is busy
R-0, HSC
R-0, HSC
GCSTAT
RBF
 2010 Microchip Technology Inc.
R-0, HSC
R-0, HSC
ADD10
TBF
bit 8
bit 0