SLB128B NSC [National Semiconductor], SLB128B Datasheet - Page 14

• Manufacturer Part Number: SLB128B
• Description: Transmitter with built-in scaler for LVDS Display Interface (LDI)
• Manufacturer: NSC [National Semiconductor]

www.national.com
OPTION SELECTION
A4M, A5M,
A6M, A7M
CLK1P
CLK1M
CLK2P
CLK2M
ID0, ID1, ID2,
ID3
ENAVDD
ENABKL
MISCELLANEOUS/TEST
GPIO1,
GPIO2,
GPIO3
CLK_INV
RES2
RES3
RES4
PWM
VSTALL
HIRQ
DS90C2501 Pin Description
Pin Name
64, 63, 62
Pin No.
46, 44,
57, 58,
42, 40
59, 60
114
113
100
49
50
37
38
69
68
70
67
66
65
I/O-LVTTL 3V
O-LVTTL 2.5
O-LVTTL 2.5
O-LVTTL 3V
O-LVTTL 3V
O-LVTTL 3V
I-LVTTL 2.5
I-LVTTL 2.5
I-LVTTL 2.5
I-LVTTL 2.5
I-LVTTL 2.5
I/O Type
O-LVDS
O-LVDS
O-LVDS
O-LVDS
O-LVDS
(Continued)
Negative LVDS differential data output for second pixel.
When DUAL pin = GND, input to D0–D11 will be coming out of A0M to A3M.
For 6-bit color application, no connect for channel A3M.
When DUAL pin =
of A0M to A3M, and the second pixel going in D0–D11 will come out of A4M
to A7M. For 6-bit color application, no connect for channels A3M and A7M.
When DUAL pin = V
A0M to A3M, the second pixel going in D12–D23 will be coming out of A4M
to A7M. For 6-bit color application, no connect for channels A3M and A7M.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
Additional positive LVDS differential clock output pin. Identical to CLK1P. No
connect if not used.
Additional negative LVDS differential clock output pin. Identical to CLK1M. No
connect if not used.
These four pins are used to select one out of 16 pre-determined LCD display
timing information. The values are from 0 to 15. This function requires support
from VBIOS or display driver. Tie these pins to GND when not in use. Tie
these four pins [ID3, ID2, ID1, ID0] to High or Low for selecting LCD panel.
ID0 is the LSB, and ID3 is the MSB. For example: 1000 will select the 9th
LCD panel.
A 4-bit register field [3:0] will be used to store the selected value for the host
to read. See PANEL field for more information.
Output to control LCD panel power under software control. Typically, this
output is used with a power switch such as a FET circuit to control LCD panel
V
Output to control LCD panel back light power under software control.
Typically, this output is used to control the enable on a backlight inverter
(Note 11).
General purpose inputs or outputs referenced to GND.
When the device is powered up, this pin defaults to an input.
When the scaler is in the power down state these signals are tri-state if
programmed as outputs (Note 11).
This pin is used to invert the polarity of the incoming pixel CLK
(CLKINP/CLKINM). A logic 0 = Normal, Logic 1 = Invert.
This pin is used in production testing and should be tied to GND in normal
operation.
This pin is used in production testing and should be tied to GND in normal
operation.
This pin is used in production testing and should be tied to GND in normal
operation.
This signal was provided for legacy support and is no longer required. This
pin should be left open in normal operation.
This signal was provided for legacy support and is no longer required. This
pin should be left open in normal operation.
This signal was provided for legacy support and is no longer required. This
pin should be left open in normal operation.
CC
(Note 11).
14
1
⁄
2
CC
V
CC
, the first pixel going in D0–D11 will be coming out of
, the first pixel going in D0–D11 will be coming out
Description