TSI-1 AGERE [Agere Systems], TSI-1 Datasheet - Page 55

• Manufacturer Part Number: TSI-1
• Description: 1k x 1k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Revision 3
September 21, 2005
Table 7-3. Data_Store_Time_Slot_Capture_Select (Read/Write)
For diagnostic and other purposes, a single incoming time slot can be sampled and made available to be read from the mi-
croprocessor interface. This register specifies which time slot will be sampled.
Table 7-4. Data_Store_Captured_Data (Read Only)
This register contains data sampled in two consecutive frames from the time slot specified in
Data_Store_Time_Slot_Capture, see Table 7-3. This register is continually updated every frame (alternating high/low byte
each frame).
Agere Systems Inc.
Address
Address
0x01142
0x01144
15:13 Unused.
15:8 Captured_Data_1. Data captured from the time slot specified by
12:0 Data_Store_Time_Slot_Capture. Specifies which time slot should be captured (sampled)
7:0
Bit
Bit
(0—8,191). This value is a function of the stream (CHI) number, the data rate of the CHI, the
time-slot offset of the CHI (RTO), and the desired time slot (TS) of the CHI. The following
algorithms can be used to determine the value for this field:
Data_Store_Time_Slot_Capture (see Table 7-3). This field is updated every other frame
alternating with Captured_Data_0. Depending on when this is read by the microprocessor, it
may be either from the frame before or after that sampled in Captured_Data_0.
Captured_Data_0. Data captured from the time slot specified by
Data_Store_Time_Slot_Capture (see Table 7-3). This field is updated every other frame
alternating with Captured_Data_1. Depending on when this is read by the microprocessor, it
may be either from the frame before or after that sampled in Captured_Data_1.
For a 16 Mbits/s CHI:
— (32 x [(TS + RTO) mod 256]) + CHI, where TS and RTO range from 0—255.
For an 8 Mbits/s CHI:
— (32 x [([2 x (TS + RTO)] + 2) mod 256]) + CHI, where TS and RTO range from 0—127.
For a 4 Mbits/s CHI:
— (32 x [([4 x (TS + RTO)] + 6) mod 256]) + CHI, where TS and RTO range from 0—63.
For a 2 Mbits/s CHI:
— (32 x [([8 x (TS + RTO)] + 14) mod 256]) + CHI, where TS and RTO range from 0—31.
Name/Description
Name/Description
1k x 1k Time-Slot Interchanger
Default
Default
0x0000
TSI-1
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—
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