TSI-1 AGERE [Agere Systems], TSI-1 Datasheet - Page 38

• Manufacturer Part Number: TSI-1
• Description: 1k x 1k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

TSI-1
1k x 1k Time-Slot Interchanger
Table 6-16. PLL_Control (Read/Write)
This register provides control over the PLL filter parameters. This register is unaffected by software reset.
Table 6-17. Power_Control (Read/Write)
To minimize power consumption when parts of the device are not used in any given application, individual sections of the
device may be powered off.
Note: All contents and information in a section that is powered off may be lost.
Table 6-18. Invalid_Address_Trap (Read Only)
Table 6-19. Scratch_Register (Read/Write)
38
38
Address
0x0000E 15:11 Unused.
Address
Address
Address
0x00010
0x00012
0x00014
15:1 Unused.
15:0 Invalid_Address. This register traps the value of an invalid address during a microproces-
15:0 Scratch_Pad. This register is for test and diagnostics purposes. It is not connected to any
9:7
6:4
3:1
Bit
10
Bit
Bit
Bit
0
0
Reserved.
Loop_Filter_Resistor. These bits provide loop filter resistor control over the PLL. The loop
filter damping resistor is approximately (Loop_Filter_Resistor + 1) x (20 kΩ). This field is only
enabled if Enable_PLL_Control is set to a 1. If Enable_PLL_Control is set to 0, default val-
ues are used within the PLL.
VCO_Gain_Control. These bits provide control over the VCO gain in the PLL. The gain is
approximately (VCO_Gain_Control x 100 MHz/V). This field is only enabled if
Enable_PLL_Control is set to 1. If Enable_PLL_Control is set to 0, default values are used
within the PLL.
Charge_Pump_Current. These bits provide control over the charge pump in the PLL.
Charge_Pump_Current is approximately (Charge_Pump_Current + 1) x (2 µA). This field is
always enabled. The typical value is 0x4.
Enable_PLL_Control. This bit is the master control for user programmability of the PLL loop
parameters. If set to 1, the VCO_Gain_Control and Loop_Filter_Resistor bit fields in this reg-
ister are allowed to serve as loop filter parameters for the PLL. If set to 0, these fields are ig-
nored and the PLL uses default values.
0 = Disable user loop parameters.
1 = Enable user loop parameters.
Data_Store_Enable. This bit enables the data store. For low-power mode, the data store can
be disabled. However, if the CHI interface is used, this bit should be set to 1. If none of the
CHIs are used, this bit can be set to 0 to save power.
0 = Data store disabled.
1 = Data store enabled.
sor access.
internal functions. Therefore, it can be used during early testing to establish that the connec-
tions between the device and the microprocessor are intact, without affecting the configura-
tion of the device.
Name/Description
Name/Description
Name/Description
Name/Description
Data Sheet, Revision 3
September 21, 2005
Agere Systems Inc.
Default
Default
Default
Default
0x0000
000
000
100
—
—
—
—
0
0