L200BB55RD AMD [Advanced Micro Devices], L200BB55RD Datasheet - Page 16

• Manufacturer Part Number: L200BB55RD
• Description: 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
14
Figure 2. Temporary Sector Unprotect Operation
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Unprotect Completed
Program Operations
Temporary Sector
Perform Erase or
RESET# = V
RESET# = V
(Note 1)
(Note 2)
START
ID
IH
D A T A S H E E T
Am29LV200B
against inadver tent writes (refer to Table 5 for
command definitions). In addition, the following hard-
ware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during V
power-up and power-down transitions, or from system
noise.
Low V
When V
accept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent uninten-
tional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
IL
, CE# = V
CC
CC
Write Inhibit
is less than V
IH
or WE# = V
IL
LKO
and OE# = V
CC
. The system must provide the
is greater than V
LKO
IH
. To initiate a write cycle,
21521D6 October 10, 2006
, the device does not
IH
during power up, the
LKO
.
CC
CC
CC