IR3897 IRF [International Rectifier], IR3897 Datasheet - Page 23

• Manufacturer Part Number: IR3897
• Description: 4A HIGHLY INTEGRATED SUPLRBUCK
• Manufacturer: IRF [International Rectifier]

T
T
VREF
This pin reflects the internal reference voltage which is
used by the error amplifier to set the output voltage. In
most operating conditions this pin is only connected to an
external bypass capacitor and it is left floating. A 1nF
ceramic capacitor is recommended for the bypass
capacitor. To keep stand by current to minimum, Vref is
not allowed to come up until EN starts going high. In
tracking mode this pin should be pulled to GND. For
margining applications, an external voltage source is
connected to Vref pin and overrides the internal reference
voltage. The external voltage source should have a low
internal resistance (<100Ω) and be able to source and sink
more than 25µA
ABLE
RACKING AND
Figure 14: Typical waveforms in tracking mode of operation:
Normal
(Non‐sequencing,
Non‐tracking)
Simultaneous
Sequencing
Ratiometric
Sequencing
Simultaneous
Tracking
Ratiometric
Tracking
2:
Operating
1.2V
(a)
(b)
R
Mode
EQUIRED
23
S
Vcc
EQUENCING
(a) simultaneous, (b) ratiometric
C
ONDITIONS FOR
AUGUST 08, 2012 |DATA SHEET | Rev 3.3
Soft Start (slave)
Vref=0V (slave)
Enable (slave)
(Floating)
(Slave)
(F
0.5V
0.5V
0.5V
Vref
Vo2 (slave)
0V
0V
Vo2 (slave)
IG
.
12)
S
IMULTANEOUS
Ramp up
Ramp up
Ramp up
Ramp up
from 0V
from 0V
from 0V
from 0V
Floating
Vp
Single‐Input Voltage, Synchronous Buck Regulator
Vo1 (master)
Vo1 (master)
/R
Condition
R
R
Required
R
R
A
A
=R
>R
F
F
ATIOMETRIC
/R
/R
R
R
=R
>R
E
E
―
C
C
/R
/R
B
B
/R
/R
C
C
>R
>R
/R
/R
F
F
D
D
E
E
D
D
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/
4A Highly Integrated SupIRBuck
POWER GOOD OUTPUT (TRACKING,
SEQUENCING, VREF MARGINING)
IR3897 continually monitors the output voltage via the
sense pin (Vsns) voltage. The Vsns voltage is an input to
the window comparator with upper and lower threshold of
0.6V and 0.45V respectively. PGood signal is high
whenever Vsns voltage is within the PGood comparator
window thresholds. The PGood pin is open drain and it
needs to be externally pulled high. High state indicates that
output is in regulation.
The threshold is set differently at different operating
modes and the results of the comparison sets the PGood
signal. Figures 15, 16, and 17 show the timing diagram of
the PGood signal at different operating modes.Vsns signal
is also used by OVP comparator for detecting output over
voltage condition.
Vref
Vsns
PGood
PGood
Vsns
0
0
0
Vp
0
0
0
0.4V
0.5 V
Figure 15: Non‐sequence, Non‐tracking Startup
1.28ms
1.28ms
Figure 16: Vp Tracking (Vref =0V)
and Vref Margin (Vp pin floating)
0.9*Vp
0.85*Vp
0.9*Vp
1.2*Vp
1.28ms
TM
IR3897
PD‐97663
1.2*Vref
Latch
OVP
0.3V