IR3897 IRF [International Rectifier], IR3897 Datasheet - Page 21

• Manufacturer Part Number: IR3897
• Description: 4A HIGHLY INTEGRATED SUPLRBUCK
• Manufacturer: IRF [International Rectifier]

FEED‐FORWARD
Feed‐Forward (F.F.) is an important feature, because it can
keep the converter stable and preserve its load transient
performance when Vin varies in a large range. In IR3897,
F.F. function is enabled when Vin pin is connected to PVin
pin. In this case, the internal low dropout (LDO) regulator is
used. The PWM ramp amplitude (Vramp) is proportionally
changed with Vin to maintain Vin/Vramp almost constant
throughout Vin variation range (as shown in Fig. 10). Thus,
the control loop bandwidth and phase margin can be
maintained constant. Feed‐forward function can also
minimize impact on output voltage from fast Vin change.
The maximum Vin slew rate is within 1V/µs.
If an external bias voltage is used as Vcc, Vin pin should be
connected to Vcc/LDO_Out pin instead of PVin pin. Then
the F.F. function is disabled. A re‐calculation of control
loop parameters is needed for re‐compensation.
SMART LOW DROPOUT REGULATOR (LDO)
IR3897 has an integrated low dropout (LDO) regulator
which can provide gate drive voltage for both drivers.
In order to improve overall efficiency over the whole load
range, LDO voltage is set to 6.4V (typ.) at mid‐ or heavy
load condition to reduce Rds(on) and thus MOSFET
conduction loss; and it is reduced to 4.4 (typ.) at light load
condition to reduce gate drive loss.
The smart LDO can select its output voltage according to
the load condition by sensing switch node (SW) voltage. At
light load condition when part of the inductor current
flows in the reverse direction (DCM=1), V
falling edge in a switching cycle. If this case happens for
consecutive 256 switching cycles, the smart LDO reduces
its output to 4.4. If in any one of the 256 cycles, Vsw < 0 on
LDrv falling edge, the counter is reset and LDO voltage
doesn’t change. On the other hand, if Vsw < 0 on LDrv
falling edge (DCM=0), LDO output is increased to 6.4V. A
hysteresis band is added to Vsw comparison to avoid
Figure 10: Timing Diagram for Feed‐Forward (F.F.) Function
21
AUGUST 08, 2012 |DATA SHEET | Rev 3.3
Single‐Input Voltage, Synchronous Buck Regulator
SW
> 0 on LDrv
- 21 -
4A Highly Integrated SupIRBuck
chattering. Figure 11 shows the timing diagram. Whenever
device turns on, LDO always starts with 6.4V, then goes to
4.4V/6.4V depending upon the load condition. For
internally biased single rail operation, Vin pin should be
connected to PVin pin, as shown in Figure 11b. If external
bias voltage is used, Vin pin should be connected to
Vcc/LDO_Out pin, as shown in Figure 11c.
OUTPUT VOLTAGE TRACKING AND SEQUENCING
IR3897 can accommodate user programmable tracking
and/or sequencing options using Vp, Vref, Enable, and
Power Good pins. In the block diagram presented on page
3, the error‐amplifier (E/A) has been depicted with three
positive inputs. Ideally, the input with the lowest voltage
LDO
Vcc/
IL
0
0
Figure 11b: Internally Biased Single Rail Operation
Figure 11a: Time Diagram for Smart LDO
Figure 11c: Use External Bias Voltage
6.4V
256/Fs
...
...
TM
4.4V
...
IR3897
PD‐97663
6.4V
...