L5953_07 STMICROELECTRONICS [STMicroelectronics], L5953_07 Datasheet
L5953_07
Related parts for L5953_07
L5953_07 Summary of contents
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Features ■ PWM: adjustable 2.5/10V - 1A switching voltage regulator ■ External POWER MOS ability for output current enhancement ■ Synchronization function ■ REG1- Linear low drop 3.3/5V - 250mA STBY voltage regulator (low current consumption) with RESET ■ REG2- ...
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Contents Contents 1 Block diagram and electrical specifications . . . . . . . . . . . . . . . . . . . . . . 6 2 Functional description . . . . . . ...
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L5953 6.3 External components for PWM regulator . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.1 6.3.2 6.3.3 6.4 Free-wheeling diode . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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L5953 List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block diagram and electrical specifications 1 Block diagram and electrical specifications Figure 1. Block diagram S1 VOLTAGE WARNING HSD1 HSD2 VSPI SPI INTERFACE IRQ Q Table 2. Absolute maximum ratings Symbol DC operating supply voltage V DD Transient supply over ...
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L5953 Figure 2. PIN connections Table 4. PIN function Pin number 1 FGND RES DGND 13 IRQ 14 HSD2 15 ...
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Block diagram and electrical specifications Table 4. PIN function (continued) Pin number 21 N.C. 22 GND 23 VSW 24 GATEIN 25 GATEOUT 26 STRAP 27 SYNC 28 VLR 29 VIN 30 FBLR 31 COMP STCAP 34 VSPI ...
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L5953 Table 5. Electrical characteristics (continued) (T Symbol Parameter h Efficiency SVR Supply voltage ripple rejection Oscillator f Switching frequency 1 f Switching frequency 2 Δf Voltage stability of switching -------- - ΔV frequency i Δf Temperature stability of switching ...
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Block diagram and electrical specifications Table 5. Electrical characteristics (continued) (T Symbol Parameter V Input voltage IN ΔV Load regulation load ΔV Line regulation line V Voltage reference ref,REG2 I Current limit Lim SVR Supply voltage rejection HSD1 V Saturation ...
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L5953 Table 5. Electrical characteristics (continued) (T Symbol Parameter I Reset output leakage RH V Delay comparator threshold CTth Delay comparator threshold V CThy hysteresis Timing capacitor output source I CT1 current Timing capacitor output pull-down R CT2 equivalent resistor ...
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Block diagram and electrical specifications Table 7. SPI interface (continued) Symbol Alt DC characteristics (T = -40 to 85°C, V amb I Input leakage current LI I Output leakage current LO V Input low voltage IL V Input high voltage ...
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L5953 Figure 4. SPI clocking scheme S (MODE 0: CPOL=0,CPHA= (MODE 3: CPOL=1,CPHA= Figure 5. Output timing ADDR.LSB IN D Figure 6. Serial input timing S C tDVCH D Q Block diagram and ...
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Functional description 2 Functional description 2.1 REG1 stand-by regulator The stand-by regulator selectable by means of the ADJ pin: - leaving the ADJ pin open, the output voltage is 5V; - connecting the ADJ pin to the Vstby pin the ...
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L5953 2.6 PWM step down voltage regulator The switching regulator as a direct duty cycle) Buck regulator: the error signal coming from the error amplifier is compared with a sawtooth to set on and off times of the power switch. ...
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Internal pin connections 3 Internal pin connections Figure 7. Linear regulators Figure 8. Reset Figure 9. Low voltage warning block diagram. 16/31 V REF POWER MOS 1.275V V STBY V STBY CONTROLLER LINEAR REGULATOR CONTROLLER POWER MOS V REF 1.275V ...
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L5953 Figure 10. HSD Figure 11. PWM Figure 12. SPI & IRQ HSD1 CONTROLLER HSD2 CONTROLLER ERROR AMPLIFIER CURRENT SENSING VREF 1.275V PWM CONTROLLER FROM THE OSCILLATOR SPI INTERFACE Internal pin connections HSD1 POWER MOS HSD1 VDD-LIN POWER MOS HSD2 ...
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SPI interface 4 SPI interface 4.1 Signals description The SPI interface available inside L5953 is able to work both in Mode 0 and Mode 3. Serial output (Q). The output pin is used to transfer data serially out of the ...
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L5953 . Table 8. Instruction set Instruction WREN WRDI WSTA RDIA RSTA . Table 9. Status register s15 s14 s13 s12 s11 REG HSD HSD TBD TBD Table 10. Status register description REG2 linear voltage s15 regulator ...
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SPI interface . Table 11. Diagnostic register d7 d6 Test mode HSD1W1 . Table 12. Diagnostic register description 20/ HSD1W2 HSD1W3 HSD2W1 The diagnostic register is referred to a ...
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L5953 5 Summary of the main operations 5.1 Operation A ● Test mode diagnostic procedure start ● 1) WREN instruction ● 2) WSTA instruction 5.2 Operation B ● Read the diagnostic register Case1: after a test mode diagnostic procedure start ...
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Summary of the main operations 5.7 Operation G ● Write operation disabled 1) WRDI instruction 5.8 Operation H ● Read the diagnostic register case 3: after an IRQ pin activation 1) RDIA instruction 2) Diagnostic register output The delay between ...
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L5953 Figure 16. Diagnostic procedure start (after write enable latch sequence operation Figure 17. Read the diagnostic RegisterCase2: during the normal working of the L5953 (after a diagnostic procedure start, see S ...
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Summary of the main operations 5.9 IRQ - Interrupt request pin ● open drain pin activated (low) every time a variation occurs in the diagnostic register. Purpose: to alert the μP that one or more warning bit ...
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L5953 6 Application note Figure 20. Block and application diagram S1 W1 VOLTAGE WARNING HSD1 HSD1 HSD2 VSPI SPI INTERFACE IRQ Q D Figure 21. Block diagram and application with external power MOS S1 W1 VOLTAGE WARNING HSD1 HSD1 HSD2 ...
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Application note Part list on evaluation board C1 = 470 μ 470 μF ESR=65 mΩ 2.2 kΩ 1.5 kΩ 180 μH 6.1 REG1 output voltage ...
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L5953 6.3.3 Output capacitor selection The criteria for the selection of the capacitor C7 is based on the output voltage ripple requirements. The ripple on the output voltage is due to a capacitive contribute, often negligible, equal to and a ...
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Application note 1. Fix the cross-over frequency f where f is the minimum switching frequency sw,min 2. Calculate the high frequency error amplifier gain 3. Chose R3 and calculate The value for R3 has not to be very high (for ...
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L5953 7 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner ...
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Revision history 8 Revision history Table 13. Document revision history Date 25-Mar-2003 04-Sep-2007 30/31 Revision 1 Initial release. 2 Layout changes and text mofifications. L5953 Changes ...
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L5953 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...