S-1701A2728-M5T1G SII [Seiko Instruments Inc], S-1701A2728-M5T1G Datasheet - Page 43

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S-1701A2728-M5T1G

Manufacturer Part Number
S-1701A2728-M5T1G
Description
HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR WITH RESET FUNCTION
Manufacturer
SII [Seiko Instruments Inc]
Datasheet
HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR WITH RESET FUNCTION
Rev.2.4
2. Delay circuit
3. Delay circuit output voltage detection type (S-1701 Series D/ E/ F/ K/ L/ M/ U/ V/ W types)
The delay circuit delays the output signal from the time when the SENSE voltage (V
the release voltage (+V
signal is not delayed when V
Figure 37 ).
The delay time (t
constant current an a capacitor, and counter.
If the input voltage or load current changes transiently, an undershoot or overshoot occurs in the
output voltage of the regulator. In the product types in which the output voltage of the regulator is
detected by the detector, if the output voltage is the detection voltage or lower due to the undershoot,
the detector operates and a reset signal may be output. To prevent this, set the value of the input-
and-output capacitor of a regulator so that the undershoot is the minimum value or set a voltage
range that allows the difference between the output voltage and detection voltage to be equal to or
greater than the undershoot.
_00
Remark The above figure shows the case when the SENSE pin is connected to VIN.
D
Hysteresis width (V
) is a fixed value that is determined by a built-in clock generator which consists of
DET
) when V
V
SENSE
IN
(V
Seiko Instruments Inc.
HYS
SENSE
SENSE
goes below the detection voltage (−V
)
Figure 37 Operation
(1) (2)
V
)
SS
is turned on (refer to point B in Figure 37 ). The output
A
(3)
(4)
B
(5)
t
D
Detection voltage (−V
Minimum operating voltage
Release voltage (+V
V
V
Output from VDOUT pin
DD
SS
DET
DET
DET
) (refer to point A in
)
)
S-1701 Series
SENSE
) exceeds
43

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