VFC101JN BURR-BROWN [Burr-Brown Corporation], VFC101JN Datasheet - Page 5

• Manufacturer Part Number: VFC101JN
• Description: Synchronized VOLTAGE-TO-FREQUENCY CONVERTER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

THEORY OF OPERATION
The VFC101 voltage-to-frequency converter provides digi-
tal output pulses with an average frequency proportional to
the analog input voltage. The output is an active low pulse
of constant duration, with a repetition rate determined by the
input voltage. Falling edges of the output pulses are synchro-
nized with rising edges of the clock input.
Operation is similar to a conventional charge-balance VFC.
An input operational amplifier (Figure 1) is configured as an
integrator so that a positive input voltage causes an input
current to flow in C
ramp negatively. When the output of the integrator crosses
the reference voltage (5V), the comparator trips, activating
the clocked logic circuit. Once activated, the clocked logic
awaits a falling edge of the clock input, followed by a rising
edge. On the rising edge, switch SW
complete clock cycle, causing the reset current, I
to the integrator input. Since I
current, I
during the one clock cycle reset period. The clocked logic
circuitry also generates a VFC output pulse during the reset
period.
Unlike conventional VFC circuits, the VFC101 accurately
derives its reset period from an external clock frequency.
This eliminates the critical timing capacitor required by
FIGURE 1. Basic Voltage-to-Frequency Operations.
V
Integrator 5V
IN
0 to 5V
0 to 8V
NOTE: (1) Pin 8 connected to pin 5.
Pin Number
0 to 10V
Clock
INPUT
IN
7
10
10
, the output of the integrator ramps positively
8
9
7
7
9
6
(1)
f
O
8
10k
FULL-SCALE VOLTAGE
4k
INT
10k
16k
. This forces the integrator output to
2.5V
10V
V
10V
8V
5V
RS
Ground
Analog
1
5
–V
SW
Integrator
is larger than the input
1mA
I
1
CC
C
1
INT
1
16
is closed for one
4
1
, to switch
Comparator
18
17
TTL/CMOS
f
5
CLOCK
other VFC circuits. One period (from rising edge to rising
edge) of the clock input determines the integrator reset
period.
When the negative-going integration of the input signal
crosses the comparator threshold, integration of the input
signal will continue until the reset period can start (awaiting
the necessary transitions of the clock). Output pulses are
thus made to align with rising edges of the external clock.
This causes the instantaneous output frequency to be a
subharmonic of the clock frequency. The average frequency,
however, will be an accurate analog of the input voltage.
A full-scale input causes a nominal output frequency equal
to one-half the clock frequency. The transfer function is
f
Input voltages greater than V
to limit at half the clock frequency. Negative inputs cause all
output pulses to cease. The full-scale input voltage, V
determined by the input pin used—see Figure 1.
One of the useful functions made possible by the VFC101’s
multiple input resistors is shown in Figure 2. By connecting
one 10V input to the 5V V
functions as a bipolar input. A –5V to +5V input range
causes a zero to f
ratio matching and temperature tracking of the input resis-
tors provides improved stability of the half-scale offset.
13
OUT
= (V
Reference
Clocked
Logic
5V
IN
20
/2V
FS
) f
CLOCK
CLOCK
/2 output frequency range. Accurate
One-Shot
.
Output
+V
REF
CC
+V
2
12
+V
0.1µF
output, the other 10V input pin
FS
CC
CC
VFC101
cause the output frequency
–V
CC
11
–V
CC
0.1µF
+V
14
15
L
Ground
Digital
0 to f
0.1µF
f
OUT
CLOCK/2
FS
, is
®