TC72-2.8MMF MICROCHIP [Microchip Technology], TC72-2.8MMF Datasheet - Page 10
![no-image](/images/no-image-200.jpg)
TC72-2.8MMF
Manufacturer Part Number
TC72-2.8MMF
Description
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.TC72-2.8MMF.pdf
(24 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TC72-2.8MMFTR
Manufacturer:
MICROCHIP
Quantity:
12 000
TC72
TABLE 3-3:
3.4
The temperature and control register data is outputted
from the TC72 using the CE, SCK and SDO lines.
Figure 3-3 shows a timing diagram of the read opera-
tion. Communication is initiated by the chip enable (CE)
going high. The SDO line remains at the voltage level
of the LSb bit that is outputted and goes to the tri-state
level when the CE line goes to a logic low level.
3.5
Data is clocked into the Control register in order to
enable the TC72’s power saving shutdown mode. The
write operation is shown in Figure 3-3 and is
accomplished using the CE, SCK and SDI line.
DS21743A-page 10
Write (A7 = 1)
Read (A7 = 0)
Note 1: CP is the Clock Polarity of the microcontroller system clock. If the inactive state of SCK is logic level high,
Disable
Mode
2: During a Read operation, SDO remains at a high impedance (High Z) level until the eight bits of data begin
Read Operation
Write Operation
CP is equal to ‘1’; otherwise, if the inactive state of SCK is low, CP is equal to ‘0’.
to be shifted out of the Temperature register.
OPERATIONAL MODES
CE
H
H
L
CP=1, Data Shifted on Falling Edge,
Data Clocked on Rising Edge
CP=0, Data Shifted on Rising Edge,
Data Clocked on Falling Edge
CP=1, Data Shifted on Falling Edge,
Data Clocked on Rising Edge
CP=0, Data Shifted on Rising Edge,
Data Clocked on Falling Edge
Input Disabled
SCK (Note 1)
FIGURE 3-2:
Operation.
CP = 0
CP = 1
SCK
SCK
CE
CE
Input Disabled
Data Bit Latch
SDI
X
SHIFT
EDGE
SHIFT
EDGE
Serial Clock Polarity (CP)
2002 Microchip Technology Inc.
CLOCK
EDGE
CLOCK
Next data bit shift,
EDGE
Note 2
High Z
High Z
SDO