BD62013FS ROHM [Rohm], BD62013FS Datasheet - Page 5

• Manufacturer Part Number: BD62013FS
• Description: Three phase brushless fan motor controller
• Manufacturer: ROHM [Rohm]

http://www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 · 15 · 001
BD62013FS
12) Thermal shutdown (TSD) circuit
13) Under voltage lock out (UVLO) circuit
14) Hall signal wrong input detection
15) Motor lock protect
16) Internal voltage regulator
The TSD circuit operates when the junction temperature of the controller exceeds the preset temperature (175°C
nominal). At this time, the controller forces all driver outputs low. Since thermal hysteresis is provided in the TSD circuit,
the chip returns to normal operation when the junction temperature falls below the preset temperature (150°C nominal).
The TSD circuit is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or
guarantee its operation in the presence of extreme heat. Do not continue to use the IC after the TSD circuit is activated,
and do not use the IC in an environment where activation of the circuit is assumed.
To secure the lowest power supply voltage necessary to operate the controller, and to prevent under voltage
malfunctions, a UVLO circuit is built into this controller. When the power supply voltage falls to V
controller forces all driver outputs low. When the voltage rises to V
operation and returns the chip to normal operation.
The voltage monitor circuit is built into for the VREG pin voltage (4.0V nominal) and HB pin voltage (3.5V nominal).
Therefore, the UVLO circuit does not release operation when either voltage rising is delayed behind the VCC voltage
rising even if VCC voltage becomes V
Hall element abnormalities may cause incorrect inputs that vary from the normal logic. When all hall input signals go high
or low, the hall signal wrong input detection circuit forces all driver outputs low. And when the controller detects the
abnormal hall signals continuously four times or more a motor rotation, the controller forces all driver outputs low and
latches the state. It is released that if the duty control voltage VSP is forced ground level once.
When the controller detects the motor locking during the fixed time (4sec. nominal, each edge of the hall signal doesn't
input either), the controller forces all driver outputs low in the under in fixed time (20sec. nominal), and self-returns to the
normal operation. This circuit is enabled the voltage force to VSP over the duty minimum voltage V
the motor cannot starts up when the controller doesn’t detect the motor rotation by the minimum duty control.
The internal voltage regulator VREG is output for the bias of the hall
element, the phase control setting. However, when using the VREG
function, be aware of the I
ground in order to stabilize output, a 1µF or lower capacitor should be
used. In this case, be sure to confirm that there is no oscillation in the
output.
OMAX
value. If a capacitor is connected to the
UVH
or more.
5/20
UVH
Fig. 6 VREG output pin application example
or above, the UVLO circuit ends the lockout
TSZ02201-0828ABB00030-1-2
R1
HW
HU
HV
VCC
VREG / HB
HWP
HWN
HUP
HUN
HVP
HVN
01.JUN.2012 Rev.001
Controller IC
SPMIN
UVL
, and note that
Datasheet
Datasheet
or below, the