A29800TM-55 AMICC [AMIC Technology], A29800TM-55 Datasheet - Page 5

• Manufacturer Part Number: A29800TM-55
• Description: 1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

Word/Byte Configuration
The
operate in the byte or word configuration. If the
is set at logic ”1”, the device is in word configuration, I/O
I/O
If the
configuration, and only I/O
by
used as an input for the LSB(A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the
selects the device.
array data to the output pins.
the time during read operation. The internal state machine
is set for reading array data upon device power-up, or after
a hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to
the AC Read Operations table for timing specifications and
to the Read Operations Timings diagram for the timing
waveforms, l
the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive
to V
sector, multiple sectors, or the entire device. The Sector
Address Tables indicate the address range that each sector
occupies. A "sector address" consists of the address inputs
required to uniquely select a sector. See the "Command
Definitions" section for details on erasing a sector or the
entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which
is separate from the memory array) on I/O
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
I
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
PRELIMINARY
CC2
0
CE
CE
IL
are active and controlled by
BYTE
in the DC Characteristics table represents the active
, and
BYTE
and
and
OE
pin determines whether the I/O pins I/O
OE
OE
CC1
pin is set at logic “0”, the device is in byte
. I/O
to V
in the DC Characteristics table represents
pins to V
(May, 2001, Version 0.0)
IH
OE
8
-I/O
. An erase operation can erase one
14
is the output control and gates
IL
0
.
-I/O
are tri-stated, and I/O
CE
WE
7
CE
are active and controlled
is the power control and
should remain at V
and
OE
7
- I/O
WE
.
0
. Standard
BYTE
15
and
15
pin is
-I/O
IH
CE
pin
15
all
0
-
5
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of the
The device enters the CMOS standby mode when the
& RESET pins are both held at V
is a more restricted voltage range than V
enters the TTL standby mode when
while RESET is held at VCC 0.5V. The device requires the
standard access time (t
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I
current specification.
Output Disable Mode
When the
disabled. The output pins are placed in the high impedance
state.
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives
the RESET pin low for at least a period of t
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.
The RESET pin may be tied to the system reset circuitry.
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
RESET
OE
CC3
in the DC Characteristics tables represents the standby
input.
7
- I/O
: Hardware Reset Pin
OE
0
. Standard read cycle timings and I
input is at V
CE
) before it is ready to read data.
AMIC Technology, Inc.
IH
, output from the device is
CC
A29800 Series
0.5V. (Note that this
CE
IH
is held at V
RP
.) The device
, the device
CC
read
CE
IH
,