HIP6004ACB INTERSIL [Intersil Corporation], HIP6004ACB Datasheet - Page 8

• Manufacturer Part Number: HIP6004ACB
• Description: Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor
• Manufacturer: INTERSIL [Intersil Corporation]

together as possible. Please note that the capacitors C
and C
Locate the HIP6004A within 3 inches of the MOSFETs, Q
and Q
source connections from the HIP6004A must be sized to
handle up to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
close to the SS pin because the internal current source is
only 10 A. Provide local V
GND pins. Locate the capacitor, C
to the BOOT and PHASE pins.
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
amplifier (Error Amp) output (V
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
PHASE node. The PWM wave is smoothed by the output
filter (L
The modulator transfer function is the small-signal transfer
function of V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage V
Modulator Break Frequency Equations
F
The compensation network consists of the error amplifier
(internal to the HIP6004A) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
LC
OUT
C
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
SS
SS
=
FB
O
-------------------------------------- -
2
2
) is regulated to the Reference voltage level. The error
O
. The circuit traces for the MOSFETs’ gate and
each represent numerous physical capacitors.
. The goal of the compensation network is to provide
HIP6004A
and C
L
0dB
1
GND
OUT
O
LAYOUT GUIDELINES
O
) and adequate phase margin. Phase margin
C
).
/V
O
E/A
LC
BOOT
PHASE
V
C
. This function is dominated by a DC
CC
BOOT
and a zero at F
CC
+12V
2-69
O
F
and C
decoupling between V
ESR
C
E/A
D
VCC
1
BOOT
OSC
) is compared with the
=
O
--------------------------------------- -
2
), with a double pole
.
ESR
as close as practical
ESR C
+V
Q
Q
1
1
2
IN
. The DC Gain of
IN
) divided by the
L
O
IN
C
O
O
at the
CC
IN
V
ss
and
OUT
1
IN
HIP6004A
is the difference between the closed loop phase at f
180 degrees The equations below relate the compensation
network’s poles, zeros and gain to the components (R
R
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
Figure 8 shows an asymptotic plot of the DC-DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the output
filter and is not shown in Figure 8. Using the above
guidelines should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds
the compensation gain. Check the compensation gain at
F
F
1. Pick Gain (R
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
3
Z1
Z2
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER COMPEN-
, C
=
=
V
1
OSC
, C
-------------------------------- -
2
--------------------------------------------------- -
2
2
OSC
ST
, and C
R
ND
ST
ND
1
R
2
SATION DESIGN
1
COMPARATOR
Zero Below Filter’s Double Pole (~75% F
Pole at the ESR Zero
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
1
+
ERROR
AMP
C
DETAILED COMPENSATION COMPONENTS
V
HIP6004A
2
R
1
E/A
/R
PWM
3
3
) in Figure 7. Use these guidelines for
1
Z
+
-
COMP
) for desired converter bandwidth
FB
-
+
C
C
1
3
REFERENCE
C
DACOUT
+
2
-
R
F
F
2
DRIVER
DRIVER
P1
P2
Z
IN
=
=
FB
---------------------------------------------------- -
2
-------------------------------- -
2
Z
V
FB
IN
PHASE
R
R
(PARASITIC)
1
C
2
3
3
L
Z
R
1
C
O
IN
1
C
-------------------- -
C
3
ESR
1
1
R
C
+
3
O
V
C
C
OUT
0dB
2
2
LC
1
V
, R
and
)
OUT
2
,